[sdiy] MIDI Clock sync advice

Phil Macphail phil.macphail at liivatera.com
Mon Mar 18 10:04:37 CET 2024

> On 17. Mar 2024, at 08:54, brianw <brianw at audiobanshee.com> wrote:
> This is a good point. I think that most hardware PLL expect the two clocks to be much closer than 1:2
Most high frequency PLLs only discriminate phase to minimise time delay (and therefore dead-time) through the phase detector. If a capture range greater than 2:1 is required then a second stage of ‘memory’ is added to the phase detector, to detect two or more pulses of one signal in the period of the other one. I think the 4046 implements this kind of phase detector, and if you want a proper study of this then the Rohde book “Digital PLL Frequency Synthesisers: Theory and Design” section 4.4.4 has more information than anyone could ever wish for, including state diagrams.
> I'm also reminded of Craig Anderton's "ring modulator" circuit from his Electronic Projects for Musicians. That's the only hardware PLL I've ever built. Don't ask me how a PLL turns out to be a ring modulator…
The ring modulator is one form of phase detector

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