[sdiy] MIDI Clock sync advice

brianw brianw at audiobanshee.com
Sun Mar 17 07:54:58 CET 2024

On Mar 16, 2024, at 5:29 PM, Tom Wiltshire wrote:
> I've had a crack at the software PLL idea and I can't get it to work.
> What I don't understand is how one clock "earlier" or "later" than the other (and this difference can only ever be 180 degrees maximum, and even which of those is going on can be hard to tell) can tell you which clock is "faster" or "slower". Perhaps it might work when the clocks are very close, but we're talking about something that has to lock in over a 1:10 range. If the internal clock is at 30bpm, and the external clock is at 200bpm, what does the phase difference *really* mean?

This is a good point. I think that most hardware PLL expect the two clocks to be much closer than 1:2
Digital audio sample rates are usually from a fixed set, not totally arbitrary. I think you typically have to manually select the sample rate for it to lock, or perhaps there's a secondary system that measures the incoming clock rate and then adjusts the internal clock to be close, before the PLL can fine tune it.

I'm remembering "jam sync" where the internal clock will match an external clock, but if the external clock drops out for one or more ticks, the internal clock will continue going along at the last rate. This kind of sync certainly needs some way to know whether a missing clock is the result of cutting the rate in half, or just a missing click. I was about to say that "jam sync" may not be what we want for MIDI Clock, because I recall the term from SMPTE sync devices, but looking up the term seems very similar.


I'm also reminded of Craig Anderton's "ring modulator" circuit from his Electronic Projects for Musicians. That's the only hardware PLL I've ever built. Don't ask me how a PLL turns out to be a ring modulator...

> If you look at five different cycles (of which clock?) you get five different answers. So I still don't get it, and that's reflected in code that doesn't work. Presumably there's something I'm still missing since PLLs are old tech that clearly does work. Am I expecting it to do something it can't do? Is 1:10 too wide a lock range for a PLL to work? Does such a range require a very slow filter, perhaps? What's going on?
> The alternative approach of "measure the time, lock it in" obviously does work. That's simple. But it does leave questions hanging about what you do about phase. Is a hard reset every X clocks really the best option? We could do something cleverer...but then there's also the question of jitter in the incoming clock. You don't really want to hard-sync to clock that might not be that solid. It would be better to stick to a longer term average of the incoming pulses, but that requires something else going on.

In one sense, a longer term average is going to give the smoothest tempo. However, that seems incompatible with hard-sync, because if the hard sync occurs too frequently, there's no long term average.

To put it another way, sometimes the internal clock will have to fire *before* the incoming clock - especially if there's jitter and the internal clock has established a long-term average. At the very least, you wouldn't want to hard sync if the internal clock has just started. Maybe some sort of threshold would be needed to skip hard sync under certain conditions.

> Anyway, thanks for all the discussion thus far. There's been a lot of interesting stuff come up.
> Tom

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