[sdiy] Adding reset clock to CD4520

[brianw]

The series capacitor on the input is a high-pass filter, or DC-blocking filter. This might be fine for a clock, which has (presumably) continuously-running frequency content. I am suspicious of copying the clock input circuitry for the Reset (Gate) input, as opposed to simply designing something directly.

Try removing the capacitor, and probably the 100k sink. The Reset may not work with a DC-blocking capacitor. I suspect that the circuit is working only once per power-up because of the capacitor. Also, knowing the minimum and maximum voltages on the Vertical Reset In should inform the correct values for the 68kΩ and 33kΩ divider. You probably want to maintain some series resistance between the input and the base of the 2N5179.

As for Pete's comment about pull-ups and pull-downs, this really depends upon the inverter chosen, and is probably why Didrik asked what is being used for the inverter. If the inverter is an Open Collector type, then it absolutely needs a pull-up because it will not drive a high voltage at all.

The starting point for CD4000 Series design is to grab the data sheets, and study the various requirements for the input pins (and outputs, while you're at it). Just because they're "digital" doesn't mean they treat all possible inputs as pure '1's and '0's.

Brian


On Jun 21, 2024, at 4:49 PM, Pete Hartman wrote:
> I have an opinion, I will let the more experienced shoot me down if I'm wrong (and will learn from the experience!)
> 
> I've seen CMOS sequencing circuits where you needed pull ups or pull downs *at the chip* to make them behave well.  You'll note that you do have the pull up on the clock directly connected to the chip.  Since the reset is active high, I would put another pull up resistor on the other side of that inverter, or possibly simply use another transistor stage wired in the same way as an inverter, to drive the reset pins.  (in other words, instead of a chip inverter, another transistor with the signal from the previous collector going to the new one's base, same pull up, same ground on the emitter, and connect the collector/resistor junction to the reset pins).
> 
> I'd say it's at least worth a test....
> 
> Pete
> 
> On Fri, Jun 21, 2024 at 5:43 PM Didrik Madheden wrote:
>> What are you using for the inverter? What value for the capacitor? Is the first and second input pulse identical? 
>> 
>> Have you worked your way backward and seen how far your pulse goes before disappearing, if it does? Do you have a pulse before/after the inverter?
>> 
>> /Didrik
>> 
>> On Sat, 22 Jun 2024, 00:06 denshi wrote:
>>> im trying to add a reset to a CD4520 but running into an issue:
>>> 
>>> in the TKB serge uses a CD4520 to handle the vertical clock (cycling between four vertical rows of pots)
>>> here is a relevant snippet of the schematic (as found on hyperreal)
>>> i copy and pasted the clock input to use as the “vertical reset” and am sending that to an inverter to the bottom half reset - it works, but only once, and then not again until i power cycle. am i missing something simple here?
>>> 
>>> <1719007181137blob.jpg>
>