[sdiy] Signals leaking into the PSU?

[Roman Sowa]

W dniu 2023-02-20 o 18:10, A.M. Barrio via Synth-diy pisze:
>
>   * To René Schmitz, Roman Sowa: I must note that the schematic I
>     attached on the first email is not the LFO, but the clock, that's
>     my bad again. That's why there's only one LED. However I just
>     noticed that I didn't rectify the signal before plugging it to
>     U1C, so the negative cycles are indeed going nowhere. I will
>     change that in the clock circuit.
>
LFO, or clock, still that's basicaly the same oscillator. SQR LFO is 
actually very useful.
Not really sure why you want to rectify anything before going t U1C. If 
you rectify it there, the LED will be on all the time. BTW, there are a 
few more pitfalls on that schematics too.

>   *  I'm still concerned about the LEDs however... a total of 7 LEDs
>     might take around 140mA,
>
not at all! 7 LEDS will take only as much as you let them to. I'd say 
3-7mA total. Before you put any LED on any instrument, play with power 
supply and resistors to find the brightness that looks perfect. Not too 
bright, not too dim. And then use this resistor in the circuit, not 330 
ohms like it was 1980.

>   * would that be correct? Even if I were to correctly bypass all my
>     circuits and properly isolate everything, would the LEDs still
>     suppose an issue in terms of sag/wiggle for a PSU that can supply
>     much more? (all of the PSUs I tried with can supply around 1A max).
>
every varying current will affect the power line, even the tiny one. 
It's only a matter how much. Blinking LEDs are one reason, and the 
saddest one. Because all they do is just for the looks. One way of 
removing LED ripple is to drive them all from current sources and 
regulate individual LED's current by clamping transistor across it. This 
way the current draw is always constant, even if hundreds of LEDs blink 
like crazy with blinding light.

>   * To Mike Beauchamp, Chris McDowell, Roman Sowa: The VCO design
>     comes from Moritz Klein's one. I'm attaching a schematic of the
>     exact circuit I'm implementing. After reading all
>
so I see that supply voltage dependency is not your biggest problem here.
But it's a good start.

>   * be put into the next VCO I put together. About this: /If you need
>     help deciding which ones those are, post the VCO schematics./
>     Would you mind pointing them out? I mentioned a
>
everything that connects to +12. Leave the opamp supply at +12, but the 
everything else with +12V arrow is affecting frequency. It's not going 
to be high performance VCO anyway, so don't bother looking for $40 
reference with impressive stability. Anything that holds stable 10V will 
be fine, even 7810. It does not have to be 10V either, 5V will be fine too.
>
>   * couple spots above, but I'd like to make sure I cover them all.
>     That being said, I'd love to hear about the reference voltages.
>     Chris, thanks for the IC examples, I'll check them out. Besides, I
>     have some spare 7805 regulators at home. Although they are quite
>     big, would they do the job for testing before I go ahead and grab
>     some of the examples you mentioned?
>
7805 is good starting point

> So, to summarize: I must look for a way to improve my bus board (uh 
> consider spending some money on a proper PSU/bus board). I must plug 
> 100uF to 470uF caps between each rail and GND on every module as well 
> as the bus board.
no you don't. It will only mess up with PSU, especially if it's 
switching supply.
One 470uF on entire bus sounds fine and it looks nice. And if you follow 
busboard fashion trends on social media, you may notice that adding a 
couple of tiny poor quality electrolytic caps on crappy busboard is 
called now a "filtering busboard". Don't fall for that.

> 100nF caps between each IC and GND are recommended. Sensitive parts of 
> circuits should never be tied directly to the power rails, but to a 
> voltage regulator instead. Would these measures remove (or at least 
> notably reduce) the problem I'm facing?

yes!
Especially think about poor 40106 in VCO. On every ramp reset slope that 
little chip is ripping its guts out to pull those heavy caps (320nF in 
total) all the way up to 12V. There will be current spikes of around 
20mA I guess, with nothing between them. That's a vacant job for big 
decoupling cap.

Roman