[sdiy] Generating a large number of CV outputs

[David Kantowitz]

... and 2nd-order sigma delta.  I might have the algorithm
[image: image.png]
[image: image.png]

def sigdelt2(bitdepth, copies):
    a = np.zeros((pow(2,bitdepth)+1, pow(2,bitdepth)*copies), dtype=np.uint)
    maxval = pow(2,bitdepth)
    for i in range(0,maxval+1):
        # s(t) = input(t) + 2 * e(n-1) - e(n-2)
        # e(t) = s(t) - output(t)
        # output(t) = s(t) >= maxval ? 1 : 0
        e_1, e_2 = 0,0
        for t in range(0,a.shape[1]):
            s = i + 2 * e_1 - e_2
            out = 1 if (s >= maxval) else 0
            e_2 = e_1
            e_1 = s - maxval*out
            a[i,t] = out
    return a

plt.figure(figsize=(16,16))
plt.imshow(sigdelt2(8, 1), cmap='binary', origin='lower')
plt.figure(figsize=(16,4))
plt.imshow(sigdelt2(8, 4), cmap='binary', origin='lower')

On Mon, Dec 11, 2023 at 7:35 PM David Kantowitz <dkantowitz at gmail.com>
wrote:

> This has been a lively topic. Here's a plot of the "bit reversed pwm":
>
> [image: image.png]
> [image: image.png]
>
>
> and python snippet to update the .ipynb:
> def mwp(bitdepth, copies):
>     """bit reversed pwm"""
>     a = np.zeros((pow(2,bitdepth)+1, pow(2,bitdepth)*copies),
> dtype=np.uint)
>     maxval = pow(2,bitdepth)
>     for i in range(0,maxval+1):
>         for t in range(0,a.shape[1]):
>             acc = t%(maxval)
>             b = '{:0{w}b}'.format(acc, w=bitdepth)
>             rev = int(b[::-1], 2)
>             a[i,t] = rev < i
>     return a
> plt.figure(figsize=(16,16))
> plt.imshow(mwp(8, 1), cmap='binary', origin='lower')
> plt.figure(figsize=(16,4))
> plt.imshow(mwp(8, 4), cmap='binary', origin='lower')
>
> On Mon, Dec 11, 2023 at 7:05 PM brianw <brianw at audiobanshee.com> wrote:
>
>>
>>
>> On Dec 11, 2023, at 9:04 AM, Vladimir Pantelic wrote:
>> > On 12/11/23 17:00, Mike Bryant wrote:
>> >> Using SPI requires continuous mode which I'm not sure most STM32s
>> support.
>> >
>> > should be no isssue when doing circular DMA (and the source memory can
>> keep up)
>>
>> The limitation is not pulling data from memory via DMA, but placing that
>> data on the SPI bus given a clock rate. 16-bit data takes at least 16
>> clocks for the data, plus maybe another clock for a gap between words,
>> depending upon how the two sides (CPU and external device) are designed.
>>
>> I believe that Mike is using the phrase, continuous mode, to refer to SPI
>> transfers that do not lose a clock cycle between words. i.e. Every clock
>> cycle has data, with no gap, and thus continuous data.
>>
>>
>> Beyond merely the various interpretations of SPI for general
>> communications, there's also the serial digital audio bit stream busses
>> that are common. Those tend to have a clock signal, a data bit, a word sync
>> bit, and sometimes a channel sync bit. For digital audio CODECs, every
>> clock is accompanied by a new data bit. The word sync keeps each audio
>> sample separate, usually by asserting at or before the first bit of each
>> new word. The channel sync bit is used for stereo and other multichannel
>> streams, and is asserted for the first channel in the sequence, usually
>> left for stereo, or Channel 0 for multichannel. I think there's never a gap
>> for dedicated digital audio streams.
>>
>> Regular SPI protocols that aren't specifically for audio usually don't
>> have the extra bits for synchronizing words and thus they have to use some
>> other technique to know which bits belong together in a sample value.
>> Sometimes that's done by flipping the Chip Select between each word,
>> sometimes it's with a gap in the data, or the devices simply count clocks
>> and thus will get way out of sync if a single clock is missed.
>>
>> Brian
>>
>>
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>
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