[sdiy] Generating a large number of CV outputs

Mon Dec 11 06:30:49 CET 2023

Python notebook attached.  Very unsophisticated code; only intended to draw
the pictures.
Uses numpy ... basically matlab in python.

On Sun, Dec 10, 2023 at 2:33 PM Mike Bryant <mbryant at futurehorizons.com>
wrote:

> Interesting and enlightening proof.
> Is this in C or Matlab or something that you could share so we could try
> seeing the effect of modification to the algorithms visually.
>
> ------------------------------
> *From:* Synth-diy <synth-diy-bounces at synth-diy.org> on behalf of David
> Kantowitz via Synth-diy <synth-diy at synth-diy.org>
> *Sent:* 10 December 2023 19:36
> *To:* Tom Wiltshire <tom at electricdruid.net>
> *Cc:* SDIY <synth-diy at synth-diy.org>
> *Subject:* Re: [sdiy] Generating a large number of CV outputs
>
> The carry-bit NCO technique is also equivalent to a 1-bit first order
> sigma delta DAC.  Probably doesn't make it much easier to understand, but
> it does make the design conclusions from sigma delta usable.  Ex. noise
> shaping curves, required Over Sampling Rates vs ENOB, reconstruction
> filtering (see: https://en.wikipedia.org/wiki/Delta-sigma_modulation).
>
> To help myself visualize this, I plotted the output bit patterns for each
> input level.  Both modulation algorithms (1-bit carry NCO and SD-1)
> produced the same chart.
>
> DC level is y-axis, time is x-axis.
> [image: image.png]
> Repeated 4 times to help imagine the oversampling:
> [image: image.png]
>
> For comparison basic PWM looks like:
> [image: image.png]
>
> By looking across a horizontal line, you can easily see the carry-bit
> approach has a vast reduction in low frequency content compared to PWM.
> That is, the digital signal 'noise' is being pushed into higher
> frequencies.  However, there's still plenty of repeating pattern in the
> NCO/SD-1
>
>
> On Fri, Dec 8, 2023 at 1:43 PM Tom Wiltshire <tom at electricdruid.net>
> wrote:
>
> Honestly, it's not. It's just that damn simple. The version I actually
> wrote was all hardware module set-up specific to the device, and basically
> nothing else, so wouldn't tell you anything. Turning it all into software
> loses a lot of the benefit, so doesn't make much sense, except to explain
> it.
>
> Play with some NCOs a bit, and then get them to make a single pulse when
> they wrap. And then - Bingo! You're there!
>
> If you thought something was missing, what exactly? Ask a more specific
> question and perhaps I can help fill in a blank. I well remember how weird
> this stuff seemed when I first met it, so I think I understand the position
> you're in now.
>
>
> > On 8 Dec 2023, at 21:18, cheater cheater <cheater00social at gmail.com>
> wrote:
> >
> > I don't get it. Most of the algorithm is missing.
> >
> > On Fri, Dec 8, 2023 at 10:07 PM Tom Wiltshire <tom at electricdruid.net>
> wrote:
> >>
> >>
> >>
> >> On 8 Dec 2023, at 20:30, cheater cheater <cheater00social at gmail.com>
> wrote:
> >>
> >> On Fri, Dec 8, 2023 at 5:06 PM Tom Wiltshire <tom at electricdruid.net>
> wrote:
> >>
> >>
> >>
> >>
> >> On 8 Dec 2023, at 14:41, Matthew Skala via Synth-diy <
> synth-diy at synth-diy.org> wrote:
> >>
> >> If PDM means PWM with bit-reversal before the comparison (such as Richie
> >> describes), then it does indeed lock you into a lower sampling rate, and
> >> that's one reason I skipped describing *that* technique.  But PWM with
> >> bit-reversal seems not to be what you mean when you say PDM.
> >>
> >>
> >> That's not what I meant when I said PDM, certainly.
> >>
> >> The way I generated it is using an NCO. The NCO generates a single-shot
> output pulse everytime the phase accumulator wraps.
> >>
> >> Now consider what happens with a simple 8-bit NCO. If our frequency
> increment is 2, for example, we get a single output pulse every 128 clocks,
> or 2 pulses per 256 clocks. Notice that they will be nicely spaced apart,
> not next to each other like PWM. The output frequency would be (clock
> frequency / 128) in this situation.
> >> If the increment is 8, we get a output pulse every 32 clocks, 8 pulses
> per 256 clocks, and again, they're nicely spaced out. The output frequency
> is now up to (clock /32) so there's been a big improvement, just by getting
> away from those extreme values a little bit.
> >> As the increment climbs, the accumulator wraps more and more often. At
> freq=128, every other clock is an output and we reach our maximum output
> frequency of (clock/2). As the increment goes above half, we start staying
> high for more than a single pulse, and the waveform effectively turns the
> other way up and we get a mirror image of the effect we've seen from 0-128.
> >>
> >> HTH,
> >> Tom
> >>
> >>
> >> I've read this a few times but I'm struggling to understand what's
> >> going on. Can someone type out an algorithm or something like that?
> >> Would appreciate it a lot. Thanks.
> >>
> >>
> >> Ok, it'd look something like this:
> >>
> >> phase: 16-bit variable (for example)
> >> freq: 16-bit variable (same as phase)
> >>
> >> So we do:
> >>
> >> // Increment phase accumulator
> >> phase = phase + freq
> >>
> >> // Did phase wraparound?
> >> If (phase>65535) { // There are probably better ways to do this test,
> if it's even required.
> >> // Ok, phase wrapped
> >> phase = phase % 65536
> >> // output a pulse a single clock in length
> >> <this is implementation dependent!>
> >> }
> >>
> >> All you need to do is run this code at a fast clock rate and you're
> off. Of course, the better way is if you can hand some of this overhead to
> hardware, and some modern uPs include NCOs as a peripheral and can be set
> up for this "single shot pulse output" mode, which means that the while
> thing boils down to simply updating the "freq" frequency increment variable
> with your current output. It's dead simple.
> >>
> >>
> >> There's a page about NCOs in general on my website:
> >>
> >> https://electricdruid.net/direct-digital-synthesis/
> >>
> >> HTH,
> >> Tom
> >>
> >>
>
>
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