[sdiy] Generating a large number of CV outputs

[mskala at northcoastsynthesis.com]

On Fri, 8 Dec 2023, Mike Bryant wrote:

> Yes the key thing about PDM over other methods is it doesn't have to have a
> fundamental fairly low sampling rate like PWM or D-S.  This gives it much
> faster response time to requested changes.  One way to think of it is that
> PWM and D-S have a low pass filter on their feedback loops, which D-S
> actually does have, whilst PWM sort of has in the lag of changing the M-S
> ratio.

I'm not sure it's true that delta-sigma has to have a fundamental fairly
slow sampling rate (more precisely:  ratio between clock rate and sample
rate exponential in the number of bits) like PWM.  I think the ability to
change the output much faster than PWM can is one of the specific
advantages of delta-sigma over PWM, as I wrote:

   If you change the target voltage for a delta-sigma DAC, you have the
   opportunity to make the output change much sooner than with PWM. With
   PWM, you basically have to wait until the next sample cycle; but a
   delta-sigma DAC asked to produce a lower target output voltage can
   drive the output low as soon as the next clock tick to start converging
   on the new value.  Whereas PWM couldn't possibly reproduce an output
   signal at a higher frequency than half the sampling rate (by the
   Nyquist Theorem), and the sampling rate was limited to 1/2n of the
   clock rate, with the delta-sigma DAC the highest output frequency is
   related directly to the clock rate instead.  That allows shrinking the
   clock rate from what a simple estimate based on sample rate and bit
   precision would otherwise imply.

If PDM means PWM with bit-reversal before the comparison (such as Richie
describes), then it does indeed lock you into a lower sampling rate, and
that's one reason I skipped describing *that* technique.  But PWM with
bit-reversal seems not to be what you mean when you say PDM.

-- 
Matthew Skala
North Coast Synthesis Ltd.