[sdiy] undertone series oscillator sync

Dakota Melin dksynth at gmail.com
Wed Aug 9 15:47:52 CEST 2023


I'm very happy with the transition cleanness with this circuit, it seems
that using two flip flops in series to sanitize things helps. The
DUSG-style "dirty undecidedness" is also great, but I can get that with a
bit of noisy modulation now! The VCF method using pole feedback for areas
of chaotic response and then locking into subharmonic/undertone series from
Rob Hordijk is fascinating as well. I've been trying to combine overtone
and undertone locking methods into "maps" of harmonic relationships that I
can then explore with my sequencers.

If you are interested in the "single cycle" mode, where the secondary is
only allowed to cycle once after every cycle of the primary and then stops,
you use that "sync monitor" logic signal as the sync source. As soon as a
cycle of the secondary finishes, it goes high and freezes the secondary at
0V.

-dk

On Wed, Aug 9, 2023 at 6:29 AM ulfur hansson <ulfurh at gmail.com> wrote:

> hi dakota,
>
> your design is wonderful!! very clean transitions and smooth tones ... and
> your explanation is exactly what i was looking for!
>
> thanks for sharing so kindly.
>
> i'm also happy to see your design also incorporates an SSI chip - these
> little critters are gamechangers, thats for sure! btw i also saw your
> filter design on your page, those formants! amazing!!
>
> i'll get on with prototyping and report on my progress 🥰
>
> best,
>>
> sent from outer space
>
> On 9 Aug 2023, at 01:39, Dakota Melin <dksynth at gmail.com> wrote:
>
> 
> hi úlfur
>
> I made a VCO partially inspired by some of Rob Hordijk's work and writings
> about his approach.
>
> I wasn't aware that he made a VCO that specifically did the undertone
> series but I am excited to check that out ... do you have an example? He
> certainly explained some ways to do it with VCFs in the blippoo box white
> paper and maybe he showed some ways to do it with VCOs somewhere?
>
> I made a brief video on the ins and outs here:
> https://www.youtube.com/watch?v=ouVBSq3MYxE
>
> I've attached a flowchart I put together.
> (PS It's only 133K file. Hope you don't mind...)
>
> The VCO uses two SSI2131 chips locked together, one as a free running
> primary VCO and the other as a permanently synced secondary VCO.
> I used some logic for the undertone series so that when the secondary is
> lower in pitch than the primary it smoothly transitions from sync'd sounds
> into undertone locking.
> There are different modes and in one mode I use that "hold" feature you
> mentioned.
>
> I think there are many ways to do the "pulse skipping" that the
> undertone/subharmonic series needs but here is what I used:
>
> Two flips flops in series. The first has the data line tied high, it is
> clocked by the EOC of the secondary VCO and it is cleared when the
> secondary VCO is reset.
> The first flip flop is what I call my "sync monitor". It monitors the
> secondary VCO and outputs a logic high when at least one cycle has been
> completed.
> This "sync monitor" is the data input for my next flip flop. It is clocked
> by the primary VCO's EOC and it is also cleared when the secondary VCO is
> reset.
> The second flip flop is the actual sync source. If the "sync monitor"
> signal is high, the next primary VCO EOC pulse clocks it through, which
> resets the secondary VCO and clears both flip flops.
>
> I use the SSI2131's PW set for a very thin pulse as my EOC/End Of Cycle,
> bumped up to the appropriate logic level. The dual flip flop logic idea was
> suggested by some friends that are also on this list, I think it first came
> up as a 4013 circuit on a slew limiter/function generator we were working
> on. This VCO uses 74HCS74 flip flops which simplify some things with
> schmitt-trigger inputs.
>
> -dk
>
> On Tue, Aug 8, 2023 at 9:46 AM Mattias Rickardsson <mr at analogue.org>
> wrote:
>
>> Hi Úlfur!
>>
>> Sorry if I'm unaware of some intricate implementation here, but isn't it
>> just ordinary softsync?
>>
>> Resetting the slave oscillator under the condition that it has spent
>> "almost" all its cycle results in the slave locking to integer undertones
>> of the master.
>>
>> /mr
>>
>>
>> Den tis 8 aug. 2023 15:22ulfur hansson via Synth-diy <
>> synth-diy at synth-diy.org> skrev:
>>
>>> hello list!
>>>
>>>
>>> i'm working on implementing the SSI2130 into a monosynth i'm building.
>>>
>>>
>>> i'm quite curious about sync capabilities, as the chip can "hold" the
>>> oscillator core hostage at 0v while hardsync input is held high.
>>>
>>>
>>> i'm interested in understanding how rob hordijk and others have managed
>>> to sync two oscillators together in order to produce an "undertone" series,
>>> if the slave osc is set to lower frequency than the master.
>>>
>>>
>>> i imagine it involves some sort of logic to work - anybody tried this?
>>>
>>>
>>> in a previous experiment i achieved this using a discrete sawtooth core,
>>> but i still don't really understand how it works or is different from
>>> regular hardsync!
>>>
>>>
>>> my brain is overheating.
>>>
>>>
>>> any thoughts would be greatly appreciated-
>>>
>>> many thanks!
>>>
>>> -úlfurh
>>>
>>> sent from outer space
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> <signal flow.png>
>
>
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