[sdiy] Using dual BBD chips for higher clock frequency

Mike Bryant mbryant at futurehorizons.com
Fri Jun 17 00:11:51 CEST 2022

Note that it is not a doubling of noise as they are (mostly) uncorrelated so it should only be a 3dB-ish change.
You could add more BBDs in parallel and sum the outputs to reduce it again.

If lowest clock speed is 20k, you really need to be filtering out everything about 10k.

-----Original Message-----
From: Synth-diy [mailto:synth-diy-bounces at synth-diy.org] On Behalf Of Didier Leplae via Synth-diy
Sent: 16 June 2022 23:02
To: Neil Johnson
Cc: Synth-diy Mailing List
Subject: Re: [sdiy] Using dual BBD chips for higher clock frequency

In an electro smash article about BBD’s, he mentions using dual BBD chips multiplexed to increase clock speed. He refers to the SAD1024 data sheet for more info. Unfortunately, I haven’t found a complete version of this yet, but I did find the first page in which they mention the same thing. 
Maybe I’m misunderstanding how this is done? Would they not be in series then.

Doubling the clock sped would bring my lowest clock speed to 20k. Then I could set LP filters to around 18k which would mostly filter out inaudible frequencies. 
The doubling of noise inherent to the chip is concerning though..

> On Jun 16, 2022, at 7:16 AM, Neil Johnson <neil.johnson71 at gmail.com> wrote:
> Hi,
> Didier Leplae wrote:
>> I'm currently working on a bucket brigade delay module using the MN3205 chip. The circuit is based on the Jan Hall article in Electronotes 87 (except using MN3205).  I'm interested in trying to add a second MN3205 chip in series in order to double the clock frequency thus reducing clock noise issues. Has anyone had experience doing this?
> All you achieve by running at a higher clock is moving the noise out 
> of the audio band.  It is still there, just less audible.  At 4096 
> stages you already have huge amounts of noise, and with limited 
> headroom your SNR is going to be pretty poor.
>> 1) Do I need to put any sort of buffering between Chip#1 & Chip#2?
> Not usually.
>> 2) Do I need a biasing trim pot before each chip? Or just Chip#1?
> Yes.  The output stage of the first chip do not preserve the bias, and 
> anyway the bias of chip #2 is not guaranteed to the same as for #1.
>> 3) Do I need to connect both outputs of Chip#1 through a clock null trim into Chip#2?
> That would be advisable.
>> 4) I'm using a PIC chip to generate the clocks. Would I need to put any sort of buffering to isolate the clock inputs of the two chips?
> Definitely.  As Mike says that's a helluva lot of capacitance to 
> drive.  And you need the inverted clock as well so you might as well 
> do the inverting and buffering externally.  Especially with two chips, 
> that'll put almost 6nF on each clock line.
> Neil

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