[sdiy] Using dual BBD chips for higher clock frequency

Michael E Caloroso mec.forumreader at gmail.com
Thu Jun 16 07:23:36 CEST 2022


Chaining BBD devices increases the noise.  I recommend using a compander in
your design.

MC

On Wed, Jun 15, 2022 at 7:38 PM Didier Leplae via Synth-diy <
synth-diy at synth-diy.org> wrote:

>
> Oops, I see I mis-numbered my questions. Here is the message with
> questions properly numbered [image: Emoji]:
>
> I'm currently working on a bucket brigade delay module using the MN3205
> chip. The circuit is based on the Jan Hall article in Electronotes 87
> (except using MN3205).  I'm interested in trying to add a second MN3205
> chip in series in order to double the clock frequency thus reducing clock
> noise issues. Has anyone had experience doing this?
>
> Here are a few questions I have:
>
> 1) Do I need to put any sort of buffering between Chip#1 & Chip#2?
>
> 2) Do I need a biasing trim pot before each chip? Or just Chip#1?
>
> 3) Do I need to connect both outputs of Chip#1 through a clock null trim
> into Chip#2?
>
> 4) I'm using a PIC chip to generate the clocks. Would I need to put any
> sort of buffering to isolate the clock inputs of the two chips?
>
> On Wednesday, June 15, 2022, 06:27:51 PM CDT, Mike Bryant <
> mbryant at futurehorizons.com> wrote:
>
>
> I’ve never used that device, but on your last point it does have a lot of
> capacitive load so may be best to use a buffer to isolate the PIC from the
> load, in which case use a dual buffer anyway.
>
>
>
>
>
>
>
> *From:* Synth-diy [mailto:synth-diy-bounces at synth-diy.org] *On Behalf Of *Didier
> Leplae via Synth-diy
> *Sent:* 16 June 2022 00:17
> *To:* Synth-diy Mailing List
> *Subject:* [sdiy] Using dual BBD chips for higher clock frequency
>
>
>
> I'm currently working on a bucket brigade delay module using the MN3205
> chip. The circuit is based on the Jan Hall article in Electronotes 87
> (except using MN3205).  I'm interested in trying to add a second MN3205
> chip in series in order to double the clock frequency thus reducing clock
> noise issues. Has anyone had experience doing this?
>
>
>
> Here are a few questions I have:
>
>
>
> 1) Do I need to put any sort of buffering between Chip#1 & Chip#2?
>
>
>
> 2) Do I need a biasing trim pot before each chip? Or just Chip#1?
>
>
>
> 3) Do I need to connect both outputs of Chip#1 through a clock null trim
> into Chip#2?
>
>
>
> 2) I'm using a PIC chip to generate the clocks. Would I need to put any
> sort of buffering to isolate the clock inputs of the two chips?
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