[sdiy] Digital Audio CODEC config help

[Mike Bryant]

No the MCLk is never needed to be edge synchronised with the other clocks on any device I have seen, just an exact multiple of them.  MCLk drives the digital logic as you say but the data is sampled, input and output on the edge of FS.  The best devices actually multiply FS input and don't even need MCLk.

And a studio master clock is always 96kHz, except in the CD mastering studio or a video suite. That should be fed directly via a suitable logic level converter to the FS input for highest performance.  You can then PLL it up for the other clocks.

On 23 Aug 2022 11:45, rburnett at richieburnett.co.uk wrote:
On 2022-08-23 08:58, Mike Bryant wrote:
> Note that the MCLK can have large amounts of jitter on it and still
> not be an issue.   BCLK is also relatively immune.  It is the FS input
> that must be absolutely jitter free so this is the track to route
> first with guard tracks each side and if possible under it as well.

I find this statement confusing for two reasons:

1. I thought that it is the MCLK that generates the edges that are used
for the ADC or DAC's oversampling process and noise shaping trickery.
So I had always believed that if there was jitter on this signal it
would really mess up the audio output quality with noise spurs either
side of wanted tones, because all of the little over-sampled periods
wouldn't be exactly the same duration.  I had assumed that this was the
reason for expensive so called low-jitter or low phase-noise audio
master clock sources in studios?

2. The BCLK and FS (LRCLK) are generated from the MCLK clock divided
down.  So how can you have a situation where there is jitter on the MCLK
and BCLK signals but the FS is totally clean?  I can't see how this is
possible.  Most CODEC data-sheets say that the MCLK, BCLK and LRCLK have
to be synchronous.  I took this to mean that LRCLK edges must line up
with BCLK and MCLK edges, as would happen if they are divided down from
the MCLK.

Is my understanding wrong?

-Richie,
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