[sdiy] Digital Audio CODEC config help

[rburnett at richieburnett.co.uk]

On 2022-08-23 08:58, Mike Bryant wrote:
> Note that the MCLK can have large amounts of jitter on it and still
> not be an issue.   BCLK is also relatively immune.  It is the FS input
> that must be absolutely jitter free so this is the track to route
> first with guard tracks each side and if possible under it as well.

I find this statement confusing for two reasons:

1. I thought that it is the MCLK that generates the edges that are used 
for the ADC or DAC's oversampling process and noise shaping trickery.  
So I had always believed that if there was jitter on this signal it 
would really mess up the audio output quality with noise spurs either 
side of wanted tones, because all of the little over-sampled periods 
wouldn't be exactly the same duration.  I had assumed that this was the 
reason for expensive so called low-jitter or low phase-noise audio 
master clock sources in studios?

2. The BCLK and FS (LRCLK) are generated from the MCLK clock divided 
down.  So how can you have a situation where there is jitter on the MCLK 
and BCLK signals but the FS is totally clean?  I can't see how this is 
possible.  Most CODEC data-sheets say that the MCLK, BCLK and LRCLK have 
to be synchronous.  I took this to mean that LRCLK edges must line up 
with BCLK and MCLK edges, as would happen if they are divided down from 
the MCLK.

Is my understanding wrong?

-Richie,