[sdiy] Digital Audio CODEC config help

[rburnett at richieburnett.co.uk]

Hi all,

The micro is Kinetis MKL26Z.  It's a Cortex M0+ specified to run at up 
to 48MHz.  The maximum supported external crystal frequency is 32MHz, so 
I could use a 24.576MHz external crystal.  However, if I clocked the 
micro directly off this I'd be throwing away almost half of the 
available MIPS.   The PLL input frequency range is 2 to 4MHz and the 
output frequency range is 48 to 100 MHz.  I could divide down the 
24.576MHz clock with the PLL pre-scaler to get it in the range 2-4MHz, 
then multiply back up to 49.152MHz or 98.304MHz in the PLL, (then divide 
by 2 in the post-scaler in the latter case to get back to 49.152MHz.)  
But this comes with any potential risks of over-clocking however small, 
if I was to come up with anything exciting enough with an M0+ that I 
wanted to put it into production! ;-)

Of course I could back off with the PLL multiplier though and go for 
something that comes in just under the 48MHz instruction rate, rather 
than just over it.

I just felt a bit un-easy about dividing the crystal oscillator down, 
only to PLL multiply it back up again with added jitter.  Then 
generating my digital audio clocks (MCLK, BCLK, LRCLK) off of this 
jittery PLL output.  But I guess I could drive the micro's SAI 
peripheral off the clean 24.576MHz crystal oscillator signal, so that 
all of the digital audio clocks are clean, and only use the PLL 
multiplied up clock to clock the micro?

-Richie,

PS. Thanks for the Kinetis SAI PDF document.  That is one of the better 
ones discussing the subject!