[sdiy] Digital Audio CODEC config help

[rburnett at richieburnett.co.uk]

Yeah, it would only be overclocked by 2.4% so probably not a problem 
given the supply voltage and temperature are well within spec.  As a 
bonus I'd get 2.4% extra MIPS from the CPU too.  (I can actually hit the 
24.576MHz MCLK output frequency without overclocking the ARM CPU, but 
the best combination of pre-/post-scaler and PLL multiplier results in 
significant under-clocking and a slice of the CPU's potential MIPS being 
thrown away.)

I just thought it was worth using a separate master clock oscillator 
module to remove any potential jitter issues with having the audio CODEC 
clocked form a MCLK that originates from a PLL multiplied up crystal.  
It also means that I don't need to de-solder and change the CPU crystal 
on the dev board, which I know from experience is a little tricky 
because it's glue spotted.

-Richie,


On 2022-08-22 19:38, Mike Bryant wrote:
> I can't believe any ARM chip will fail at 24.576 MHz if it is ok at 24
> MHz.   Just change the crystal to 24.576 or some sub-multiple of 2.
> 
> 
> -----Original Message-----
> From: Synth-diy [mailto:synth-diy-bounces at synth-diy.org] On Behalf Of
> Richie Burnett
> Sent: 22 August 2022 17:38
> To: synth-diy mailing list
> Subject: Re: [sdiy] Digital Audio CODEC config help
> 
> Worked a treat! Thanks.
> 
> I was able to generate stereo audio at 46.875kHz, 93.75kHz and
> 187.5kHz, using AK4556 with 24MHz MCLK and only changing the SAI
> divider ratios for BCLK and LRCLK in software to choose the sample
> rate.  (The strange sample rates are because the maximum frequency the
> Kinetis can generate as MCLK is 24MHz, due to CPU clock speed
> limitation.)
> 
> The SAI can be configured to be clocked from an external 24.576MHz
> MCLK signal and still act as I2S master so I'm ultimately going to go
> with that so it can hit the standard sample rates of 48/96/192 kHz.
> The 24.576MHz MCLK signal from a decent oscillator module will also
> likely have less jitter than the 24MHz signal divided down from the
> ARM CPU's PLL output!
> 
> Haven't connected the ADC part to the micro yet, but looping the
> CODEC's DOUT signal back to it's DIN pin resulted in stereo audio
> being passed through the ADC to the DAC outputs.  So, all looks good.
> 
> -Richie,
> 
> 
> 
> -----Original Message-----
> From: Mike Bryant
> Sent: Wednesday, August 17, 2022 4:19 PM
> To: Richie Burnett ; synth-diy mailing list
> Subject: RE: [sdiy] Digital Audio CODEC config help
> 
>> Am I right in thinking that my choice of Mode 8 (or your Mode 4
>> choice) would let me run the CODEC at Fs=48kHz, 96kHz, or 192kHz, with
>> a fixed MCLK frequency,
> 
> In theory yes.  MCLK should be 24.576MHz and you just alter FS to suit.
> 
> However, I recall some AKM chips had issues with running at 512x clock
> for 48kHz sampling, though I can't remember if it is this particular
> chip as I always only use 96kHz.
> 
> 
>> I also dabble with ultrasonic stuff in my day job so being able to go
>> up to 192kHz would be nice
> 
> You might get the DAC to do this, sort of, using de-emphasis mode 1,
> but the ADC will always kill anything over 20kHz I believe.  You'll
> need a different chip for that, probably an Analog Devices one.
> 
> 
> 
> 
> -----Original Message-----
> From: Synth-diy [mailto:synth-diy-bounces at synth-diy.org] On Behalf Of
> Richie Burnett
> Sent: 17 August 2022 11:52
> To: synth-diy mailing list
> Subject: Re: [sdiy] Digital Audio CODEC config help
> 
>> Yes Mode 8 should be fine for you.  I always use I2S and Mode 4 with
>> the STM version of the SAI interface, but LJ should be ok
> 
> Thanks Mike.  I was kind of heading in that direction but wanted to be 
> sure.
> 
> Am I right in thinking that my choice of Mode 8 (or your Mode 4
> choice) would let me run the CODEC at Fs=48kHz, 96kHz, or 192kHz, with
> a fixed MCLK frequency, just by re-programming the SAI on the micro?
> (This would be useful because for some projects I might want 48kHz,
> others 96kHz, and I also dabble with ultrasonic stuff in my day job so
> being able to go up to 192kHz would be nice.)
> 
> I'm trying to get my head around the difference between Mode 8 and Mode 
> 9.
> It looks like Mode 9 is for a fixed sample rate ("Normal Speed") but
> lets you use different oversampling ratios for the MCLK?  ...and
> conversely Mode
> 8 allows you to support different sample rates ("Quad Speed", "Double 
> Speed"
> & "Normal Speed") but using a fixed MCLK frequency?  Am I
> understanding this correctly?
> 
> I know that a CODEC in slave mode can determine some information about
> the ratios of the different clocks by counting the number of cycles of
> the Bit Clock and Master Clock in one cycle of the Word Clock.  The
> configuration pins presumably provide the missing information it needs
> to operate as the user desires.
> 
> -Richie,
> 
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