[sdiy] Can google's free* 180nm OSHW foundry be used for synth parts?

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On 07.08.22 08:34, cheater cheater wrote:
> So on a 180 nm node, how many transistors and other primitives can be
> fit on 1 mm^2? How does that compare to a simple full synth voice, say
> something like a Minimoog?
> 
Well, that depends. For analog applications, size of transistors and 
therefore chip size doesn't really scale with technology node the way it 
does for digital. Especially if one wants to minimize variations between 
transistors - which is nearly always the case in analog applications - 
transistors will be MUCH bigger than what the technology node suggests 
as feature size. For analog applications, I'd expect to see transistor 
lengths of 0.5 micron (500 nm) at least, in sensitive spots like current 
mirrors even 1 micron or more. Transistor width scales with current 
drive needed. For typical use, I'd guess something between 10 and 30 
micron, so we end up with something like 1 by 40 microns per transistor 
pair (nmos+pmos) including contacts. Passives will be significantly 
bigger if we want to get values we typically see in schematics with not 
too shabby variation between nominally identical devices. Take 
capacitors for example. In CMOS processes targeted at analog and 
mixed-signal applications, there very often is a dedicated MIM capacitor 
available in addition to the parasitic MOS capacitor (Gate - gate oxide 
- body). This specific process has comparably thick gate oxide for a 
logic process, it seems to be intended for 3.3V and 5V peration. MOS 
capacitance is spec'ed at 2.3 and 4.4 fF/µm² (yes, FemtoFarads per 
square micron), so 1 pF will take 300 µm², 1 mm² will get you no more 
than 3 nF effectively, and that will be nonlinear with respect to 
applied voltage, and it will be frequency-dependent. MIM capacitance is 
spec'ed at 1, 1.5 and 2 fF/µm², but linear.
Resistors will be similar: they are just by-products of transistor 
formation, and they will be made of doped gate silicon. They are spec'ed 
at 1kOhms, 2kOhms and 3kOhms per square, which indicate the process is 
more targeted at low power applications than high speed. Naively, one 
could state that the average 10k resistor could be made as small as half 
a square micron (180nm line width, 3kR/sq resistor), but they will vary 
a LOT: +/- 10% can easily be imagined without any detrimental effects 
like self heating or tempco taken into account, and matching between 
individual resistors on the same chip will be poor. Where accuracy and 
stability are of concern, one wouldn't use the highest available sheet 
resistance, which commonly is achieved by implanting both n- and p-type 
dopands so they partly compensate, and would use widths significantly 
wider than minimum. At 2kOhms/sq and 3 µm width, the mentioned 10k 
resistor would take up a total of about 50 µm² with reasonable matching 
between resistors. Absolute accuracy will still not be much better than 
before.

The main problem however will be to decide, whether or not it actually 
makes sense. I had a quick look at the schematic of the Oscillator board 
of the minimoog. Let's do a quick back-of-the-evelope calculation: 
Assuming we could get away with replacing every opamp with just three 
differential pairs (two gain stages, one pair as current mirror), and 
also could get away with replacing every bipolar transistor in the 
schematic with a MOS, or the vertical PNP included in the process would 
suit our needs, and we could simply replace the JFETs with MOSFETS, then 
we would end up with roughly 100 to 120 differential pairs at 40 µm² 
each. 100% overhead for wiring would give a nice round 10000µm² (=0.01 
mm²) for the transistors alone. This is about the same size we would 
need to take into account for one single bondpad (including spacing to 
the next pad and keepout areas). The oscillator board has about 30 
connections to the external world, most of which can not be done away 
with at this level. From what I wrote above, it is clear that we cannot 
integrate the capacitances as-is on chip, there's simply no way to get 
100pF. But, we don't need to integrate all of it: Power supply 
decoupling capacitors will be mostly off-chip in any case. For filter 
capacitors it depends: we can either put them off chip and leave the 
circuit as it is, then we'd need extra bondpads, further increasing chip 
size. Or we adapt the circuit to achieve the same frequency response 
with higher resistance and lower capacitance. After all, we hardly need 
to take bias currents of stages further down the signal chain into 
account as MOS transistor gates essentially draw none.

So, with, say 32 external connections in a square chip we'll get to a 
minimum size of 1 mm², leaving about 0.5 mm² for active circuitry and 
internal wiring. As we estimated transistor area for the oscillator at 
0.01 mm², it seems manageable to integrate most of the oscillator board 
into one single 1mm² chip, assuming we can get away with the 
modifications outlined above. There should even be some room left for 
some further refinements of the circuitry or cases where substituting a 
full opamp with just three differential pairs wouldn't cut it. The 
critical part however will be the passives.

With BGA packaging, even a small 0.4mm pitch will ask for 5 mm² unless 
some interposer packaging is employed.

Bests,
Florian