[sdiy] Can google's free* 180nm OSHW foundry be used for synth parts?

[Mike Bryant]

The key primitive you'll be missing is capacitors.  No chance of putting the sizes needed for a ladder filter on-die, so you'll need lots of pins on the package.

Given there's lots of really good VCO and VCA chips already, not sure what the advantages would be.

-----Original Message-----
From: Synth-diy [mailto:synth-diy-bounces at synth-diy.org] On Behalf Of cheater cheater via Synth-diy
Sent: 07 August 2022 07:34
To: usenet at teply.info
Cc: synth-diy at synth-diy.org
Subject: Re: [sdiy] Can google's free* 180nm OSHW foundry be used for synth parts?

So on a 180 nm node, how many transistors and other primitives can be fit on 1 mm^2? How does that compare to a simple full synth voice, say something like a Minimoog?

On Sun, Aug 7, 2022 at 1:49 AM usenet at teply.info <usenet at teply.info> wrote:
>
> On 06.08.22 23:42, cheater cheater wrote:
> > Bear in mind the Google program is a shuttle program so as I 
> > understand it that means your design shares the wafer with other 
> > people's. I think that means whatever process you'll be using is 
> > common to all of those chips so you probably can't ask for a special 
> > process, but I don't know.
> >
> That's the whole idea of a shuttle program or Multi-project wafer
> service: The mask set is fixed cost, regardless if you produce one 
> single wafer - which no fab would even consider doing - or thousands 
> of them. With the numbers Mike Bryant mentioned - which are pretty 
> average by the way for a 180nm CMOS process -, up to about 40-50 
> wafers, mask cost will dominate the total wafer manufacturing price 
> (still, backend manufacturing stuff like testing, dicing, packaging, 
> comes on top per-piece). And, for low volumes it'll dominate total 
> cost of manufacturing the chip unless you need some extra bells and 
> whistles in backend.
> If you intend to ship only few samples, maybe a few hundred, per 
> design, it'll be most cost-efficient per design if you cram as many 
> designs onto one mask set as possible and rather increase the number 
> of wafers to produce the number of samples you need. Of course that 
> only works up to a certain point, as scaling up the mask size has its 
> limits based on
> *REALLY* expensive equipment - the scanner for lithography of a 180nm 
> process will be the most expensive tool needed, costing approximately
> 20-25 million dollars. If you need bigger masks, you'll need a scanner 
> that can handle bigger masks, which become significantly more 
> expensive, and the masks itself become much more expensive as well. I 
> believe the masks commonly available tools and suppliers can handle 
> are on the order of a couple hundred square millimetres.
> Even with a 30x30mm mask area, you can cram about 300 3mm² designs - 
> which is fairly big for a 180nm cmos unless you intend to copy an 
> Intel Pentium III  or similar - onto one mask set and still get about 
> 10 complete masks per wafer. So for 100 samples per design, even 10 
> wafers would be sufficient to fulfill the need of 100 samples per 
> design. Yet the foundry probably wouldn't even start production of 
> less than 25 wafers...
>
> Of course they won't run a special process for anyone unless that 
> customer has very deep pockets.
> The parasitic bipolars I mentioned are intrinsic to the way a MOS 
> transistor is formed: with source and drain being n-doped, and the 
> body in between being p-doped, you intrinsically have an npn bipolar 
> device, which is not normally used as such because the base-emitter 
> junction is not forward biased in normal MOS operation. So the device 
> is there, if you use it or not. Its just that electrically it's going 
> to be very poor. Which is why nearly nobody cares about these kind of devices.
>
> Bests,
> Florian

_______________________________________________
Synth-diy mailing list
Synth-diy at synth-diy.org
http://synth-diy.org/mailman/listinfo/synth-diy
Selling or trading? Use marketplace at synth-diy.org