[sdiy] Issue with CD4024 Ripple Counter

David G Dixon dixon at mail.ubc.ca
Tue Sep 21 21:41:27 CEST 2021

Tim, I'd rather just solve this problem, rather than devote my life to it.
I don't design logic circuits very often (obviously).

To answer Roman's question, why only use 2 bits of a 7-bit counter, this is
because I "inherited" this circuit from Ken Stone, and that is what he used,
and I never saw a reason to change it.  I could use a 4013, but I'd probably
have the same clocking issues -- I obviously have some deep problems in my
clock circuit, so I'm going to use this as an opportunity to finally learn
something about that.  I'm going to play with the debouncing circuit a bit
to see if I can at least sort that out.  I'll also play with and RC on the
CLOCK pin (I tried a 100pF cap with the 10k resistor, but maybe I need
something else -- people are suggesting 33pF, so I'll start there).

The 4024 is supposed to have decent noise immunity on the CLOCK input, which
I would assume to mean that if I can't see anything on my old Tek scope,
then it shouldn't be a problem.  I guess I don't understand what "noise
immunity" means.  I thought it meant "immune to noise" but I guess it means
something else.

Also, I could understand if there was multiple clocking on a noisy
comparator output (but my comparator has hysteresis).  However, what I don't
understand is that there is NO clocking on what is clearly a very nice
negative clock transition, and what appears to be single clocking on the
positive transition.  How would those two things relate?  It's like you're
telling me that the patient may be having a heart attack, but he's
complaining about a broken leg.


-----Original Message-----
From: Synth-diy [mailto:synth-diy-bounces at synth-diy.org] On Behalf Of Tim
Sent: Tuesday, September 21, 2021 10:55 AM
To: synth-diy at synth-diy.org
Subject: Re: [sdiy] Issue with CD4024 Ripple Counter

[CAUTION: Non-UBC Email]

> As you can see, it is just about the cleanest transition you could 
> ever hope to see.  If that edge can't clock a CMOS chip properly,
> nothing can.

Yep, it looks lovely, especially at the relatively slow speed of 50us per
division - does it look as nice when viewed faster?

Years ago at work we had a problem with a device on a board that seemed to
be double-clocking. On the fastest scope we had (200Mhz) the clock edge
didn't look too bad at the fastest timebase setting, but did have a 'slight
deviation' in it. The engineer investigating the problem felt certain we
weren't seeing the whole story, and wanted to see it on a faster scope, but
the engineering director felt that there would be nothing more to see. After
much more head-scratching, making little progress, and a few more elapsed
weeks he relented, and we rented a scope with a much greater bandwidth,
perhaps 2 or 3 GHz or even more, and there the 'slight deviation' was seen
to be a fabulous up-down-up double-wobble that was causing all the havoc.
Lesson learned - just because your scope can't see it doesn't mean it isn't
there. (And the director agreed the faster scope _was_ valuable after all,
so we purchased it ex-rental.)

Tim Stinchcombe 

Cheltenham, Glos, UK
email: tim102 at timstinchcombe.co.uk

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