[sdiy] Issue with CD4024 Ripple Counter

Tim Stinchcombe tim102 at timstinchcombe.co.uk
Tue Sep 21 19:55:29 CEST 2021

> As you can see, it is just about the cleanest transition you
> could ever hope to see.  If that edge can't clock a CMOS chip properly,
> nothing can.

Yep, it looks lovely, especially at the relatively slow speed of 50us per
division - does it look as nice when viewed faster?

Years ago at work we had a problem with a device on a board that seemed to
be double-clocking. On the fastest scope we had (200Mhz) the clock edge
didn't look too bad at the fastest timebase setting, but did have a 'slight
deviation' in it. The engineer investigating the problem felt certain we
weren't seeing the whole story, and wanted to see it on a faster scope, but
the engineering director felt that there would be nothing more to see. After
much more head-scratching, making little progress, and a few more elapsed
weeks he relented, and we rented a scope with a much greater bandwidth,
perhaps 2 or 3 GHz or even more, and there the 'slight deviation' was seen
to be a fabulous up-down-up double-wobble that was causing all the havoc.
Lesson learned - just because your scope can't see it doesn't mean it isn't
there. (And the director agreed the faster scope _was_ valuable after all,
so we purchased it ex-rental.)

Tim Stinchcombe 

Cheltenham, Glos, UK
email: tim102 at timstinchcombe.co.uk

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