[sdiy] Issue with CD4024 Ripple Counter

Roman Sowa modular at go2.pl
Tue Sep 21 19:39:05 CEST 2021

A lot can happen during 50us. Have you checked the edges at, say 200ns/div?
Are you saying that this beautifull falling edge on 4024 pin, does NOT 
advance the counter?
Time for another crazy idea - have you checked other 4024 outputs than 
those 2 used? Maybe there is something weird going on, like ringing on 
clock input, so with every clock pulse it advances exactly 4 steps, so 
your 2 outputs of interest stay unchanged after clock pulse, but the 
rest of the counter counts nicely.

I'm tempted to etch a board according to your pictures and solder it, 
too bad I don't have 4024BE around.


W dniu 2021-09-21 o 02:48, David G Dixon via Synth-diy pisze:
> So, I built the new circuit (I've attached the schematic again here).  
> Note that I changed the 100k resistor from the diode to ground to 10k, 
> as this made the simulation results ever so slightly cleaner at the 
> transitions.
> Results: MC14024BCP and CD4024BCN are still clocking as they should.  
> CD4024BE is still clocking on the wrong edge.
> I swapped the diode and the 10k resistor just to see if that would 
> have any effect -- it didn't.  Also, I like them the way they are 
> because the keep the levels closer to the opamp output and zero.
> I've also attached a scopeshot of the falling edge, taken with the 
> probe attached to the 4024 CLOCK pin.  As you can see, it is just 
> about the cleanest transition you could ever hope to see.  If that 
> edge can't clock a CMOS chip properly, then nothing can.
> So, I'm out of ideas.  I could disconnect the 20k resistor to see if 
> the rectifier is affecting the CLOCK pin, but I honestly cannot see 
> how it could, given the very low output impedance of the TL072. The 
> comparator is more or less completely optimized now, and is performing 
> admirably.
> I guess I'll try Tim's simple clocking circuit on breadboard to see if 
> I can get that to work.  However, I'm not holding out much hope, since 
> I think it is fair to say that my comparator circuit is generating 
> what looks to be a more or less perfect clock signal.
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