[sdiy] Issue with CD4024 Ripple Counter

Tim Stinchcombe tim102 at timstinchcombe.co.uk
Tue Sep 21 11:14:36 CEST 2021


> The manual clocking switch
> is connected to the +V and GND rails, and is fed to the comparator through
a 1k
> resistor, whereas the clock input jack is connected through a 10k

...and both these connections appear to be on another board, but on this
board you have 'clock in' and 'clock out' not only on parallel traces, but
also on adjacent pins on the one header feeding them from the other board. I
really cannot think that this is a good idea, as it means there will be
_some_ coupling around the whole lot!? (And the slight differences in
behaviour between the two activation methods could well account for the
differences in behaviour...?)

Simulation may help establish how feasible this is as the cause of the
problem - I might give it a go later, but have other appointments to attend
to for most of the day.

Tim Stinchcombe 

Cheltenham, Glos, UK
email: tim102 at timstinchcombe.co.uk

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