[sdiy] Issue with CD4024 Ripple Counter

Roman Sowa modular at go2.pl
Tue Sep 21 10:16:41 CEST 2021

Why rectifier when 3 resistors would be just as good?
And if you want buffered CLKout, then maybe something like this (attached)?


W dniu 2021-09-20 o 19:18, David G Dixon pisze:
> Hi Team,
> Thanks for all of the responses.  I really do appreciate it!
> So, this little "project" has followed my normal modus operandi -- I design
> something quickly, test it, it doesn't work, I lash out, ask for help, get
> all angry -- then, at about 1:00 am, I sit down and have a fresh look and
> try to get it right.
> Lastnight I did just that.  You will find the results of my sober second
> thought attached.  I decided that the problem is a combination of stupid
> stuff.  So, the first thing I did was to disconnect the 4024 CLOCK pin from
> everything downstream.  All that stuff can be driven in parallel from the
> comparator, which has very low output impedance so won't "feel" any of it.
> Then, I turned my attention to the comparator.  I halved the hysteresis
> resistor from 1M to 499k and added a speed-up capacitor (between + and Out
> -- I've not worked with comparators all that much, so I had done this wrong
> before).  Simulation suggested that the 100pF capacitor would sharpen and
> accelerate the transitions to a nearly perfect straight line with a
> transition time of about 1 microsecond, so the comparator should now be
> perfectly conditioned to drive the CLOCK.
> Next, I turned my attention to the gate output circuit.  This one was really
> stupid.  I realized that all I needed was an inverting half-wave rectifier
> at about 50% gain to convert the 10V comparator output to a 5V gate output.
> In simulation, this works perfectly, and I've built enough rectifiers to
> know that it is pretty bulletproof.
> I also changed the layout of the offending PCB lastnight, so this morning
> I'm going to print, transfer, etch, drill, tin, stuff, and test the new
> board.  It's about 10:15 now -- I should have it done by 12:00, and I'll let
> y'all know how it worked.
> -----Original Message-----
> From: Roman Sowa [mailto:modular at go2.pl]
> Sent: Monday, September 20, 2021 1:34 AM
> To: synth-diy at synth-diy.org; dixon at mail.ubc.ca
> Subject: Re: [sdiy] Issue with CD4024 Ripple Counter
> [CAUTION: Non-UBC Email]
> The 100k resistor after the diode does not do much in here. The comparator
> output load is determined in 80% by 10k to zener and then 10k to inverter,
> so you may just remove it.
> Next, since comparator output goes to about 10V, then the zener also does
> not do anything much, because 2x10k divider gives about 5V at zeners
> cathode. So if you replace the zener and 2x 10k with just one 2k resistor
> the "clockout" will work the same.
> But why 4024 responds to positive edge at all? My only idea at this moment
> would be oscillations of opamp used as comparator caused by parasitics
> transmitting output fast jump to inverting input, that was already pointed
> by someone. Nothing obvious here.
> Roman
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