[sdiy] Issue with CD4024 Ripple Counter

Roman Sowa modular at go2.pl
Mon Sep 20 10:34:01 CEST 2021

The 100k resistor after the diode does not do much in here. The 
comparator output load is determined in 80% by 10k to zener and then 10k 
to inverter, so you may just remove it.
Next, since comparator output goes to about 10V, then the zener also 
does not do anything much, because 2x10k divider gives about 5V at 
zeners cathode. So if you replace the zener and 2x 10k with just one 2k 
resistor the "clockout" will work the same.
But why 4024 responds to positive edge at all? My only idea at this 
moment would be oscillations of opamp used as comparator caused by 
parasitics transmitting output fast jump to inverting input, that was 
already pointed by someone. Nothing obvious here.


W dniu 2021-09-19 o 07:26, David G Dixon via Synth-diy pisze:
> The ASR clock circuit is attached to this email.
> The two switches are how I am simulating the ON-OFF-(ON) switch.  When
> switch "1" is open, then the switch is in the OFF position.  When switch "1"
> is closed, then switch "0" represents the momentary switch.  This switch
> sends either 0V or 12V through a 1k resistor to the 2.2n debouncing cap.
> The signal generator represents a signal plugged into the Clock input jack
> (such as an LFO).  This comes in through a 10k resistor.  In this way, the
> switch always has priority.  They are both fed through 10k into the
> inverting input of the opamp comparator with a 100k resistor to ground to
> provide a current path.  The threshold of the comparator is set to a little
> less than 2V.  Hence, when the LFO signal rises above this threshold, or
> when the momentary switch is pressed, the comparator output is negative.
> The diode changes this to about 0V.  When the clock signal is less than
> about 2V or the momentary switch is not pressed, then the comparator output
> is positive.
> The output of the diode goes directly to the 4024 Clock pin.  This will be
> either about 10V or about 0V, and the transitions will be about 2
> microseconds.  This is dropped to ground through a 100k resistor to provide
> a current path.  This then goes through a 10k resistor to a 5.1V zener to
> fix the level at 5V, then into a unity gain inverter with a +5V level shift
> (-12V through 24k) to give a 5V gate signal for the Gate output jack.  This
> signal will have the same polarity as the incoming clock signal, even though
> the 4024 advances on the negative edge.  This output can be used to gate an
> envelope for a filter, or whatever.
> If you see any obvious mistakes, I'd love to know about it.  As I said, this
> circuit works perfectly with MC14024B, but CD4024B clocks on the wrong edge.
> -----Original Message-----
> From: Synth-diy [mailto:synth-diy-bounces at synth-diy.org] On Behalf Of m
> brandenberg
> Sent: Saturday, September 18, 2021 12:04 PM
> To: 'synth-diy mailing list'
> Subject: Re: [sdiy] Issue with CD4024 Ripple Counter
> [CAUTION: Non-UBC Email]
> On Sat, 18 Sep 2021, David G Dixon via Synth-diy wrote:
>> Also, I would remind you that I set up a test rig on breadboard, with
>> similar circuitry (an opamp comparator into a diode), and the 4024s
>> either didn't work or looked real bad (lots of hash) even though the
>> driving waveform is very clean.
> Sorry to belabor the point but the 'one diode' mention has made me twitch
> twice now.  Is that one diode feeding into a passively pulled up (or down)
> input or one diode into a floating node that might be drifting around
> metastability?
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