[sdiy] Issue with CD4024 Ripple Counter
David G Dixon
dixon at mail.ubc.ca
Sat Sep 18 20:24:30 CEST 2021
Guys, this is an ASR. It is being clocked at LFO rates, or manually with a switch. The clock signal is going through an opamp comparator -- TL072, slew rate of 13V/us, so the clock edge is about 1 to 2 microseconds, well less than the 8 us suggested in the datasheet. On the scope it looks perfect.
The CD4024 was working fine in the ASR, but was simply clocking on the wrong edge. That was the original problem. The VDD pin of the 4024 is connected to the positive rail (+15V in my rig, but eventually +12 in the eurorack product), and the opamp of course generates output two diode drops below that. This is plenty sufficient to clock the 4024. The Reset and VSS pins are connected to the 0V rail.
Also, I would remind you that I set up a test rig on breadboard, with similar circuitry (an opamp comparator into a diode), and the 4024s either didn't work or looked real bad (lots of hash) even though the driving waveform is very clean. The MC14024B behaved exactly as I expected it to, which is perfectly. Absolutely clean output waveforms.
I have built dozens of ASRs, and most of them have used CD4024. I haven't, in the past, felt the need to distinguish, or even to notice, what flavor of 4024 chip I used. I just grabbed one out of my bin, plugged it in, and if the ASR worked, then I was happy. I am now wondering whether all of my previous ASRs actually clock on the wrong edge. The only reason I noticed this time is that I have now installed a manual clocking switch, and when it triggers on the wrong edge it is very noticeable (the clocking didn't occur when I pushed the momentary switch down, but when I let it go). My latest prototype with the MC14024B is working perfectly in every respect. Hence, if I can rely on all MC14024B chips to perform similarly, then I don't see a problem.
From: Synth-diy [mailto:synth-diy-bounces at synth-diy.org] On Behalf Of Phil Macphail
Sent: Saturday, September 18, 2021 6:40 AM
To: synth-diy mailing list
Subject: Re: [sdiy] Issue with CD4024 Ripple Counter
[CAUTION: Non-UBC Email]
How fast is the chip being clocked? Could it simply be the propagation delay through the chip happens to be half the clock-period?
Sent from my iPhone
> On 18. Sep 2021, at 16:34, Ben Stuyts <ben at stuyts.nl> wrote:
>> On 18 Sep 2021, at 14:22, Phillip L Harbison <alvitar at xavax.com> wrote:
>> I would check for noise on the clock signal and noise overall. If the clock has noise, you might consider first passing it through a gate with a Schmitt trigger. If the clock transition is slow you might consider passing it through a comparator configured with some hysteresis.
> The 4024 already has schmitt-trigger input. (Not on the reset line though.) Datasheet says unlimited rise/fall time is allowed.
> Comparing the CD4024 and MC14024 datasheets, I see quite a few timing differences. I noticed that the MC14024 is quite a bit slower: (@ 15V, Max) 4 Mhz vs 12 MHz.
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