[sdiy] Issue with CD4024 Ripple Counter

David G Dixon dixon at mail.ubc.ca
Fri Sep 17 18:47:49 CEST 2021

Hi Roman,

I have a debouncing LPF on the switch, and it is currently 1k and 2.2nF.  I
started with 1k and 10nF, and that gave me only intermittent clocking of the
CD4024.  I removed the cap and also replaced it with 100pF, and that gave me
clocking on both the down and up of the switch (both edges).  2.2nF at least
gave me reliable clocking, but on the wrong edge.  The signal from the
switch and/or the input clock signal goes through the LPF (the input jack
has a 10k resistor and the switch has a 1k resistor, so that the switch
signal overtakes the jack) which are both dropped to ground through the
2.2nF cap, then they go to an opamp comparator with a threshold voltage of
+2V.  The comparator output is normally at +V but switches to -V when the
clock input signal rises above +2V.  With this arrangement, I can clock my
ASR with any LFO signal or envelope or gate, or really anything handy.  The
output of the comparator goes through a 1N4148 diode to eliminate the
negative output, is dropped through a 100k resistor to ground and then goes
into the 4024 clock input.

Both the switch and the jack reliably clock the CD4024 on the positive
transition.  I can understand that the clock signal (which is coming from a
comparator) may be too slow to clock the counter.  What I don't understand
is why the counter would, instead, reliably clock on the wrong transition.
It's stupid.  Digital electronics are stupid, which is why I typically
confine myself to analog.  I don't have the patience for all the stupid
arbitrary rules around digital devices, or the stupid coding.  F all that
stupid S!  That's what I say (but when I say it, I include the uck and the

I see on the MC14024B datasheet that that device has been designed to accept
even quite slow clock transitions, so I'm assuming that this is the reason
why it works better.  I'll just go with it.

-----Original Message-----
From: Roman Sowa [mailto:modular at go2.pl] 
Sent: Friday, September 17, 2021 1:51 AM
To: synth-diy at synth-diy.org; dixon at mail.ubc.ca
Subject: Re: [sdiy] Issue with CD4024 Ripple Counter

[CAUTION: Non-UBC Email]

Try to experiment with slew rate of input signal. Feed it with the fastest
edges clock pulse you can get, say 20ns rise time. And decouple the supply
pins of the chip generously.
If that does not help, tell me what crack you smoke, would love to try that


W dniu 2021-09-17 o 05:57, David G Dixon via Synth-diy pisze:
> Hey SDIY Team,
> I've got a device that uses a 4024 ripple counter.  The datasheet says 
> that it advances on the negative transition of the clock.  All mine
> (CD4024BE) are advancing on the positive transition of the clock.  
> However, I tried an MC14024BCP and it worked properly.
> Am I smoking crack?  Why are my CD4024s behaving opposite to the 
> datasheet, but the MC14024 is behaving as per the datasheet?  What is 
> it that I don't know about these devices?
> Cheers,
> Dave Dixon
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