[sdiy] CV/Gate delay project..

Jean-Pierre Desrochers jpdesroc at oricom.ca
Fri Jan 29 22:04:24 CET 2021


You are right Tom..

I'm looking now for at least 14bits ADC.. 16 bits will probably be.

12 bits DAC's should be fine.

Maxim MX7705EPE+ 16 bits ADC could do (I think).

 

As a note here:

I saw that synthesizers.com has a quantizer module Q171
that uses ADC/DAC process on incoming CV’s.

Here are the specs:

 

Specifications:

Panel Size: Single width 2.125"w x 8.75"h.

Quantization Method: Processor controlled ADC/DAC.

ADC Inputs: 10-bit with precision buffer/scaler.

DAC Outputs: 12-bit with precision buffer/scaler.

Gate Inputs: 0-5V minimum, rising edge.

Gate Outputs: 0-5V, 5ms on, 2ms minimum off.

Power: +15V at 30ma, -15V at 30ma, +5V at 50ma.

https://www.synthesizers.com/products/q171/q171data.pdf


The CV inputs are fed to precision opamps OPA4277
then routed to a micro MEGA644P’s  internal 10 bits ADC.

The CV outputs are from 12bits DAC’s LTC1448.


So… I’ve not tried this module but assumes it works correctly
using a micro’s internal 10bits ADC and an external 12bits DAC.. ??

 

Hmmm.

 

 

-----Message d'origine-----
De : Tom Wiltshire [mailto:tom at electricdruid.net] 
Envoyé : 29 janvier 2021 15:37
À : Jean-Pierre Desrochers
Cc : SYNTH DIY
Objet : Re: [sdiy] CV/Gate delay project..

 

I think you’ve answered your own question:

 

> around 10 steps between each semi-tone.

 

That’s 10 cents, clearly audible. E.g. Not good enough.

 

Tom

 

==================

       Electric Druid

Synth & Stompbox DIY

==================

 

 

 

> On 29 Jan 2021, at 16:28, Jean-Pierre Desrochers < <mailto:jpdesroc at oricom.ca> jpdesroc at oricom.ca> wrote:

> 

> Hi list,

> 

> I'm working on a new module for my DOTCOM modular.

> It would memorize incoming CV's and Gate's state for 2msec up to 10sec 

> then spit the stream in steps of 1msec.

> The code for Gate memorizing is done.

> I'm now wondering if using a Microchip PIC 10bits ADC is linear enough 

> to read incoming CV values (0 to 8vdc)...

> There will be an input buffer amplifier that will take care of taking 

> down the 0to8vdc to 0to5vdc for the PIC.

> Incoming CV's 0-8vdc, 12 semitones/octaves.. that makes 1024 / (8 x 12)..

> around 10 steps between each semi-tones.

> My worry is the PIC ADC linearity precision..

> The 10bits memorized values will be output using a 12bits SPI DAC.

> I have a bunch of old PIC16F88 that I want to utilize here.

> Old but still usable for SPI.

> What do you think about PIC's ADC linearity wise ?

> 

> JP

> 

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