[sdiy] CV/Gate delay project..

Mike Bryant mbryant at futurehorizons.com
Fri Jan 29 18:07:10 CET 2021


Reading once won't be good enough - you'll have a semitone of randomness.   But you could possibly read the CV several times to try to smooth it out.  But you'll never get it perfect.  Couldn't you use an SPI ADC/DAC ?

-----Original Message-----
From: Synth-diy [mailto:synth-diy-bounces at synth-diy.org] On Behalf Of Jean-Pierre Desrochers
Sent: 29 January 2021 16:28
To: 'SYNTH DIY'
Subject: [sdiy] CV/Gate delay project..

Hi list,

I'm working on a new module for my DOTCOM modular.
It would memorize incoming CV's and Gate's state for 2msec up to 10sec then spit the stream in steps of 1msec.
The code for Gate memorizing is done.
I'm now wondering if using a Microchip PIC 10bits ADC is linear enough to read incoming CV values (0 to 8vdc)...
There will be an input buffer amplifier that will take care of taking down the 0to8vdc to 0to5vdc for the PIC.
Incoming CV's 0-8vdc, 12 semitones/octaves.. that makes 1024 / (8 x 12)..
around 10 steps between each semi-tones.
My worry is the PIC ADC linearity precision..
The 10bits memorized values will be output using a 12bits SPI DAC.
I have a bunch of old PIC16F88 that I want to utilize here.
Old but still usable for SPI.
What do you think about PIC's ADC linearity wise ?
 
JP

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