[sdiy] CV/Gate delay project..

[Jean-Pierre Desrochers]

Hi list,

I'm working on a new module for my DOTCOM modular.
It would memorize incoming CV's and Gate's state for 2msec up to 10sec 
then spit the stream in steps of 1msec.
The code for Gate memorizing is done.
I'm now wondering if using a Microchip PIC 10bits ADC is
linear enough to read incoming CV values (0 to 8vdc)...
There will be an input buffer amplifier that will take care
of taking down the 0to8vdc to 0to5vdc for the PIC.
Incoming CV's 0-8vdc, 12 semitones/octaves.. that makes 1024 / (8 x 12)..
around 10 steps between each semi-tones.
My worry is the PIC ADC linearity precision..
The 10bits memorized values will be output using a 12bits SPI DAC.
I have a bunch of old PIC16F88 that I want to utilize here.
Old but still usable for SPI.
What do you think about PIC's ADC linearity wise ?
 
JP