[sdiy] Nanosecond delays - the clean or dirty method?

Brian Willoughby brianw at audiobanshee.com
Fri Feb 26 21:35:47 CET 2021



On Feb 25, 2021, at 09:31, Steve Lenham <steve at bendentech.co.uk> wrote:
> On 25/02/2021 17:17, Didrik Madheden wrote:
>> Are you sure this is actually the problem? Some FRAM chips require a new pulse on either /CS or /RD / /WR for each new access. Some MCUs on the other hand hold /CS and /RD low and just modify the address. This works for regular SRAM chips but not certain FRAM chips as mentioned. If this is the issue, what you actually need is to gate the /CS signal. This problem exists for example for the Gameboy CPU when retrofitting FRAM for the battery backed save RAM in game cartridges.
>> /Didrik
> 
> Thanks Didrik, but yes, I am sure. The problem is related to that, though.
> 
> The reason the FRAMs require a new /CS pulse for each access is that they latch the address on the falling edge of /CS and ignore any subsequent changes.
> 
> In the system I'm working on (an EMT246), the RAM cart is memory-mapped onto a good old Z80. /CS is generated by decoding the higher-order address lines and gating with /MREQ. This would all be fine BUT...they chose to buffer the address bus to the cart with a tristate buffer that is gated on and off using the RAM /CS signal.
> 
> That means the RAM /CS goes low fractionally before the valid address arrives and the FRAM latches in the wrong address. Delaying /CS a tiny bit gives the tristate buffer time to pass the address through. I've tried it and it works.

The first time I read the above, I interpreted it to mean that you could invert some signal and get the right timing. However, upon re-reading it, I think I misinterpreted.

Most systems I've seen use a master clock that can delay a signal like this by a very precise period. Of course, delaying by 25 ns would require a 40 MHz clock ... that doesn't seem like something you'd have handy.

Whether you delay by RC or gate propagation delay, you'll want to account for the wide variation of resistor values, capacitance values and/or gate propagation. Often, gates list the worst case longest propagation delay for a given power supply voltage, but that is not the same as a guaranteed minimum delay. I would be worried that any design would be at risk of having too little delay under varying operating conditions.

Others have already mentioned that some logic inputs do not like soft transitions. Others merely require that you avoid non-monotonic changes (this is where noise mixed in with the signal would cause an issue). My recollection is that most chip manufacturers only discuss this for the Reset input - probably because they expect you to use an RC for cold Reset.

Sorry for rambling,

Brian





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