[sdiy] Nanosecond delays - the clean or dirty method?

Steve Lenham steve at bendentech.co.uk
Thu Feb 25 18:31:44 CET 2021

On 25/02/2021 17:17, Didrik Madheden wrote:
> Are you sure this is actually the problem? Some FRAM chips require a new 
> pulse on either /CS or /RD / /WR for each new access. Some MCUs on the 
> other hand hold /CS and /RD low and just modify the address. This works 
> for regular SRAM chips but not certain FRAM chips as mentioned. If this 
> is the issue, what you actually need is to gate the /CS signal. This 
> problem exists for example for the Gameboy CPU when retrofitting FRAM 
> for the battery backed save RAM in game cartridges.
> /Didrik

Thanks Didrik, but yes, I am sure. The problem is related to that, though.

The reason the FRAMs require a new /CS pulse for each access is that 
they latch the address on the falling edge of /CS and ignore any 
subsequent changes.

In the system I'm working on (an EMT246), the RAM cart is memory-mapped 
onto a good old Z80. /CS is generated by decoding the higher-order 
address lines and gating with /MREQ. This would all be fine BUT...they 
chose to buffer the address bus to the cart with a tristate buffer that 
is gated on and off using the RAM /CS signal.

That means the RAM /CS goes low fractionally before the valid address 
arrives and the FRAM latches in the wrong address. Delaying /CS a tiny 
bit gives the tristate buffer time to pass the address through. I've 
tried it and it works.


Steve L.
Benden Sound Technology

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