[sdiy] Nanosecond delays - the clean or dirty method?

Richie Burnett rburnett at richieburnett.co.uk
Thu Feb 25 17:36:20 CET 2021


All seems perfectly reasonably to me Steve.

For smaller delays you can put little wiggles in the PCB trace or send the signal down a short length of transmission line. But you'd still need several metres of coax to nudge it back by just 25ns!

The slow rise time resulting from the RC circuit is not a problem in itself, but can cause problems in the presence of noise if the receiving device is fast enough to register the additional clock edges.

To be honest I've seen more problems with lightening-fast clock edges due to signal reflections. So I'd take a clock line with controlled dv/dt any day of the week :-)

-Richie, 

Sent from my Xperia SP on O2

---- Steve Lenham wrote ----

>I need to delay the Chip Enable signal to a RAM IC by a tiny amount - 
>around 25ns. I'm building a replacement memory cart for a vintage unit, 
>and this is necessary to allow the use of a battery-free F-RAM for 
>storage (some F-RAMs have certain timing quirks).
>
>I know that the proper way to do this would be to insert one or more 
>pairs of inverters to delay the signal by a few propagation delays, but 
>that needs, like, another chip.
>
>The DIRTY way to do it is to add a tiny RC delay. I tried 1K5 and 22pF 
>and it worked perfectly, delaying the edge by about 50ns and solving my 
>problem.
>
>I'm well aware of the dangers of slow pulse edges and would never 
>consider this for something more lengthy without adding a Schmitt 
>buffer, but am curious as to whether it is still seen as irredeemably 
>bad practice for a tiny nudge such as this. I'm sure I have seen it done 
>in various vintage schematics.
>
>Any thoughts would be appeciated!
>
>Cheers,
>
>Steve L.
>Benden Sound Technology
>
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