[sdiy] ADc & DAC voltage dividers.. fixed resistors values finally..

Roman Sowa modular at go2.pl
Tue Feb 16 10:24:53 CET 2021

Why not make R1=30k and R2=49.9k and skip U19A?
Or to keep input closer to 100k make it 38k and 63.4?
And I would rather use 5V rail-to-rail opamp as ADC buffer. You can 
never know if +/-15V powered opamp will not peak outside 0-5V during 
rapid powerup.

Don't worry about any offsets as long as they are stable with low 
temperature drift. Overall offset will be corrected in firmware anyway.

One more thing I would do is to alter the gains a little to have at 
least 8.1V or 8.2V working range in case all tolerances in the circuit 
will lead to lower range than expected. And also intentionally introduce 
some (20mV maybe?) negative offset at DAC buffer and same positive 
offset in ADC buffer. This will make sure working range of the system 
includes 0V. Without that it may be difficult to get closer than 5mV 
from 0 and we all know that even 0.5mV can be anoying, because that's 
about 30 times more than 1 LSB in CD audio!


W dniu 2021-02-15 o 18:22, Jean-Pierre Desrochers pisze:
> Sorry, please forget the previous email..
> The following circuit is what should be (D1,D2 displaced):
> Here is a revised version of the ADC/DAC circuits according (I think)
> to what has been suggested and pointed out such as:
> ADC’s Input bias current vs driving opamp’s output impedance
> Resulting in pour linearity of incoming CVs,
> LPF bad results on ADC readings (R1 and former C1 removed cap ).
> BTW, +5v reference will be from a REF02  0.2% precision
> and as shown will drive both ADC/DAC.
> OP275 seems to be a good choice for driving the ADC
> but I hope more buffering 2 chained opamps won’t bring too much offset 
> voltage
> to AIN input here..
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