[sdiy] Digital accumulator VCO core?

[Brian Willoughby]

How do you avoid canceling out the step itself?

Brian


On Feb 15, 2021, at 17:07, cheater cheater wrote:
> The aliased step which you worry about is cancelled out by the
> presented algorithm. Notice that in the final version the signal also
> contains a naiive aliased step - but in the opposite direction of what
> you're applying it to. The two cancel out and you're left with only
> the band limited one.