[sdiy] ADc & DAC voltage dividers.. fixed resistors values finally..

Mike Bryant mbryant at futurehorizons.com
Mon Feb 15 14:04:54 CET 2021


On some ADCs, though fortunately less nowadays, the bias current isn't even linearly related to VIN !   I suspect that might have been the issue for someone the other day who said the upper half of the range was offset to the bottom half.

As you say use an op-amp, but rather than a current limiting resistor, use a low-voltage op-amp designed for the task of driving ADCs, run it off the same supply as the ADC, and put the current limiting resistor and/or voltage limiting diodes on the input of the op-amp so as to totally isolate the ADC from the outside world.


-----Original Message-----
From: Synth-diy [mailto:synth-diy-bounces at synth-diy.org] On Behalf Of René Schmitz
Sent: 15 February 2021 12:56
To: synth-diy at synth-diy.org
Subject: Re: [sdiy] ADc & DAC voltage dividers.. fixed resistors values finally..

In addition to what Veronica wrote, you might also need to watch out for the bias current of the ADCs VIN pin.

10uA amounts to about 19mV when looking into 3.01k||4.99k. Fine if the current was constant over temperature

and the voltage range. But likely it isn't and causes errors. The solution for both (the bandwith as pointed out below, and the offset
current)

is to lower the impedance driving VIN. I would maybe move the divider ahead of the opamp, and drive the pin directly.

With a bit of protection for the VIN pin, say by current limiting the opamps output.


Best,

  René


Am 14.02.2021 um 21:43 schrieb Veronica Merryfield:
> I think your ADC input has too much resistance and capacitance to meet 16bits at 200Ksps.
>
> The input to the ADC should be treated as an RC time constant. To meet 16 bit you need 11Tc periods which need to fit 1.1us to run at the rated 200Ksps. That means RC=1.1us/11. C is 40pf in the ADC, so the input impedance should be less than 2k5. Your drive impedance is higher and you added a significant capacitor load too. Were you meaning to put a 3Khz LPF ahead of the ADC?
>
>> On Feb 14, 2021, at 2:50 PM, Jean-Pierre Desrochers <jpdesroc at oricom.ca> wrote:
>>
>> Following your wise suggestions I think the following circuit would
>> do a good job (precision & LSB kept wise).
>> On the DAC side, R5 will be in the feedback loop to keep 16 bits precision
>> and from loading the actual U19B opamp  gain. (tested today in PSPICE)
>> Tested with a load going down to 3k !
>> The auto calibration (at final design step) will give the actual
>> offset to be adjusted for ADC/DAC correct tracking.
>> As shown here a common +5VDC 0.2% reference (REF02BP)
>> will be used for both ADC & DAC for dual tracking.
>> No more trimmer..
>>   
>> One more question arises though..
>> Should I use a gain 1 buffer between the R1/R2 node
>> and U16 AIN input ??
>> Even with C24 the ADC input has a track/hold circuit..
>> but the datasheet states that MAX11100  AIN input  leakage current is 10uA worst case (40pf capacitance)..
>> And.. adding another opamp in the ADC input chain could add possible offset problems.
>> Maybe that’s ok as it is so far..
>>
>> BUT… As usual if you see something wrong please let me know..
>> Thanks.
>> JP
>>   
>> <image001.png>
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