[sdiy] ADc & DAC voltage dividers.. fixed resistors values finally..

Veronica Merryfield veronica at merryfield.ca
Sun Feb 14 21:43:10 CET 2021

I think your ADC input has too much resistance and capacitance to meet 16bits at 200Ksps.

The input to the ADC should be treated as an RC time constant. To meet 16 bit you need 11Tc periods which need to fit 1.1us to run at the rated 200Ksps. That means RC=1.1us/11. C is 40pf in the ADC, so the input impedance should be less than 2k5. Your drive impedance is higher and you added a significant capacitor load too. Were you meaning to put a 3Khz LPF ahead of the ADC?

> On Feb 14, 2021, at 2:50 PM, Jean-Pierre Desrochers <jpdesroc at oricom.ca> wrote:
> Following your wise suggestions I think the following circuit would
> do a good job (precision & LSB kept wise).
> On the DAC side, R5 will be in the feedback loop to keep 16 bits precision 
> and from loading the actual U19B opamp  gain. (tested today in PSPICE)
> Tested with a load going down to 3k !
> The auto calibration (at final design step) will give the actual
> offset to be adjusted for ADC/DAC correct tracking.
> As shown here a common +5VDC 0.2% reference (REF02BP)
> will be used for both ADC & DAC for dual tracking.
> No more trimmer..
> One more question arises though..
> Should I use a gain 1 buffer between the R1/R2 node
> and U16 AIN input ??
> Even with C24 the ADC input has a track/hold circuit..
> but the datasheet states that MAX11100  AIN input  leakage current is 10uA worst case (40pf capacitance).. 
> And.. adding another opamp in the ADC input chain could add possible offset problems.
> Maybe that’s ok as it is so far..
> BUT… As usual if you see something wrong please let me know..
> Thanks.
> JP
> <image001.png>
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