[sdiy] Digital accumulator VCO core?

Richie Burnett rburnett at richieburnett.co.uk
Wed Feb 10 10:32:13 CET 2021

Yes, that's the idea. The trick is adding just enough random modulation to break up the aliased tones, but not enough to make the pitch of the main tone noticeably unstable.


Sent from my Xperia SP on O2

---- cheater cheater wrote ----

>isn't that spread spectrum modulation? the thing we all saw in BIOS
>back in the day?
>On Tue, Feb 9, 2021 at 8:21 PM Richie Burnett
><rburnett at richieburnett.co.uk> wrote:
>> > FPGA-based approaches mentioned earlier allow very high sample rates
>> that reduce aliases into the noise floor. There are a number of newer
>> FPGAs like the Lattice ice40 series that are inexpensive and can easily
>> hit multi-MHz sample rates...
>> It's also possible to add a miniscule amount of pitch dither to the tone
>> you're synthesising so that those naive sawtooth harmonics up in the MHz
>> around the sample rate don't alias back down to the baseband with an
>> annoying discrete line spectrum.  Only a tiny amount of pitch modulation is
>> necessary to broaden the spectrum of such very high order harmonics so that
>> they all blend nicely together into the noise floor when they alias back
>> down below 20kHz.
>> -Richie.
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