[sdiy] Digital accumulator VCO core?

Richie Burnett rburnett at richieburnett.co.uk
Tue Feb 9 20:18:41 CET 2021

> FPGA-based approaches mentioned earlier allow very high sample rates
that reduce aliases into the noise floor. There are a number of newer
FPGAs like the Lattice ice40 series that are inexpensive and can easily
hit multi-MHz sample rates...

It's also possible to add a miniscule amount of pitch dither to the tone 
you're synthesising so that those naive sawtooth harmonics up in the MHz 
around the sample rate don't alias back down to the baseband with an 
annoying discrete line spectrum.  Only a tiny amount of pitch modulation is 
necessary to broaden the spectrum of such very high order harmonics so that 
they all blend nicely together into the noise floor when they alias back 
down below 20kHz.


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