[sdiy] Digital accumulator VCO core?

Tom Wiltshire tom at electricdruid.net
Tue Feb 9 10:34:00 CET 2021

One thing I don’t understand about this approach is “Why?”. What’s the *advantage* if you’re going to try and keep all the parts that create errors?

There was someone here some years ago who’d done a voltage-controlled oscillator on a dsPIC. The cunning part of that was that the output waveform was a triangle instead of a ramp. That massively reduces the aliasing problems, and since triangle-core oscillators are common, there’s a lot of wave shaper designs you can tack on the end. But the exponential conversion was done inside the chip for obvious reasons. The ADC sample rate was fast enough for it to do convincing FM.

The only synths I know of that runs oscillators at anything like 12MHz is the Novation Peak/Summit. The ‘Oxford’ oscillators in those instruments use an FPGA and a clever DAC technique to run at very high speeds and avoid the need for anti-aliasing measures. I’ve never seen it done anywhere else. The development of decent virtual analogs follows the development of good algorithms like BLEPs that enable you to produce good quality band limited ramps and  pulses *at normal sample rates*. The point of those algorithms is they work fine at 48KHz.


       Electric Druid
Synth & Stompbox DIY

> On 9 Feb 2021, at 07:46, cheater cheater <cheater00social at gmail.com> wrote:
> There's a couple reasons to measure current. First of all, this is
> core only - so the exp etc happen in analog still. And because of
> that, those electronics will act differently when fed into low
> impedance and high impedance. Hence measuring current. The issue with
> many virtual analog synths is that they think an oscillator is just a
> shaped ramp, essentially just a very simplified accumulator capacitor,
> and so they don't model all the electronics that happen around that
> capacitor. That's a problem and if you want to replace /just/ the
> accumulator with digital electronics then you should definitely also
> include all the other stuff around the oscillator, since that is also
> going to have its own character.
> When switching, what you actually want to do is to continue
> accumulating in an aliased manner, but when you're outputting, you
> instead limit the slew rate to something outside the audio range. This
> way you can avoid aliasing. You can play back a band limited sample of
> a switch, using a technique like MinBLEP etc. But at 12 MHz, who
> cares, right? You just bandlimit the thing somewhere, and you're done
> with it. (note: you might think you probably don't want to run the
> synth engine at 12 MHz, but that's what most virtual analogs run at,
> 192 kHz at 64x oversampling)
> On Tue, Feb 9, 2021 at 6:03 AM Brian Willoughby <brianw at audiobanshee.com> wrote:
>> I don't follow the need for a current stage.
>> I have designed with DAC chips that output current, but I've never seen an ADC that directly measures current. It's worth noticing that CV is a voltage, and feeding a current into a shunt resistor will convert that current back into a voltage. You might as well just feed the CV directly to the ADC of your choice. In other words, skip the current stage altogether.
>> You could even skip the ADC and just feed a digital value in via MIDI or some other digital communications channel, although I'm only suggesting that as an option in addition to a CV input.
>> If you still want the bad tempco effect, then you can use another ADC channel to read that separately, and offset or scale the CV value proportional to the "temperature."
>> You probably want to select a DSP instead of the general purpose CPU so the code can keep up with accumulating and generating internal samples at 12 MHz. Your accumulator would then be much larger than the 16-bit input, and thus the code wouldn't run out of resolution even at 12 MHz.
>> What you describe is reminding me of the Roland GR-300 voice, although that is discrete logic rather than code accumulating the values. In fact, your idea could be implemented in discrete hardware, especially if the ADC has parallel data outputs.
>> I didn't know what you meant by solid state switches until I realized that  you're talking about the reset at the end of a ramp core period. It's true that a DSP could accumulate like an op-amp and capacitor without the limitation of finite discharge time. One drawback, though, is that an instantaneous change in the accumulator value would create aliasing of infinite harmonics that would be folded back into the ramp wave - but using a wavetable would already have plenty of digital artifacts so perhaps this isn't a concern.
>> Brian Willoughby
>> On Feb 8, 2021, at 19:43, cheater cheater wrote:
>>> Hi all,
>>> I was wondering if anyone ever experimented with replacing the
>>> accumulator core with a digital setup. Essentially you would have
>>> control voltage turned into current being shunted to ground, and you'd
>>> sample this current with the ADC, accumulating it in software. A
>>> 16-bit, 12 MS/s ADC like the Cirrus Logic WM8196SCDS/V costs only ~$2
>>> - $3 depending on how many you need, and my guess is that this would
>>> be more than enough bit depth and sampling rate to preclude numerical
>>> error. I think this would be able to do FM at audio rate. So does
>>> anyone do this sort of thing?
>>> The nice thing is you don't need to use solid state switches any more,
>>> your switchover is immediate, so no tracking error due to that. Also
>>> perfect for complex wave shapes, you could have a VCO like that easily
>>> output a waveform from a wavetable while still being fully capable of
>>> FM.
>>> You might want to use a shunt resistor with bad tempco ... just to
>>> keep things feeling "analog" ...
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