[sdiy] Jupiter 8 not booting

Phillip Gallo philgallo at gmail.com
Thu Feb 4 09:13:19 CET 2021


Brian,

Exercising the "Power-On-Reset" circuit while avoiding power cycling the
unit was the point and a good idea.
Grounding the junction of r1/c8 is a great place to start.  It allows
testing of differentiator and the inverting buffer.
I would recommend grabbers over alligator clips, however.   Also, it
doesn't quite test the configuration as a POR.
After your clip analysis, you are going to toggle that circuits power.  The
POR could be symptomatic of a PS issue.

Monitoring the collector of TR1 you can see the power up slope as
differentiated to drive TR2 which inverts the direction of the raggedy
pulse as approp. for the Z80 (780).
The output cap C9 smooths the signal, suppresses simple noise and serves to
frustrate your attempts to do more than fine tune the pulse width using R2
or C7.

A wise man once said " If there is an error in the Reset circuit that is
causing TR2 to conduct - even partially - to ground ... "  Well the
collector of TR1 is a great place to start looking.
Since the condition is intermittent, sooner or later you are going to have
to test the config. as a POR.

Your point regarding the RESET pulse width is a good one since 3 clks
cycles of the applied 4MHz clock is the minimum spec.    The RESET input
high spec is 2V so the Reset Pulse looks to the micro as around 300ms or
so.  (I was surprised by the absence of a suppression diode across r4.  The
diode would also protect downstream logic.)

If the POR finally checks out and the intermittency is still there ... i
would check the battery backed RAM.  RESET qualifies (gates) the RAM chip
selects.  The chips which gates the chip selects (40H000)
has a 4V input "High" threshold ... i imagine to ensure the stability of
the circuit before allowing access to RAM.  Oddly, it connects to a linear
circuit and hasn't  a schmitt trigger input.
There is diode OR'ing of the power (bat/PS) so this reduces the threshold
by a diode drop.

Now regarding your reluctance to disturb vintage solder .. it's an opinion
easy to respect but , gee whiz, equally easy to ignore.
(Hell, i'll bet there are quite a few folks "on this very list" who have
disinterred the sacred solder of instruments famous and otherwise.)

regards,
p


On Wed, Feb 3, 2021 at 5:33 PM Brian Willoughby <brianw at audiobanshee.com>
wrote:

> There are a couple of problems with this last suggestion.
>
> 1) Pulling the end of R1 involves unnecessary soldering on vintage gear. I
> recommend against this unless absolutely necessary.
>
> 2) There are a couple of reasons why removing the rail will not reveal the
> most likely causes of this error.
>
> Reset is an Active Low signal. The RESET net node in the circuit is an
> inverted wire-OR situation. In other words, multiple parts of the circuit
> can pull the line low (active), but only one part of the circuit pulls the
> node high.
>
> a) If there is an error in the Reset circuit that is causing TR2 to
> conduct - even partially - to ground, then removing the rail supply from R1
> will not necessarily stop this. TR2 is still connected to ground and could
> possibly conduct.
>
> b) If there is any error the rest of the synth connected to Reset - as
> others have suggested - then removing the rail from R1 won't help.
>
>
> Basically, the problem is that Reset is stuck at 1.4 V and cannot get any
> higher in voltage than that. Removing the rail connection to R1 will not
> allow that voltage to get any higher unless you're lucky.
>
>
> Instead, what could be done is to hook an alligator clip to the Reset net
> node side of R1. Then, an external source could ground Reset. This would
> not diagnose all possible errors, but it does allow Reset to be activated
> without any soldering.
>
> Brian Willoughby
>
>
> On Feb 3, 2021, at 14:49, Phillip Gallo wrote:
> > Looking at you schem excerpt ...
> >
> > You can pull the rail end of R1 and connect it thru a switch to the pos
> rail.
> > Doing this you can operate the power up reset at will.
> >
> > Switch closed and everything quiescent  T1 collector should be ~
> 80-100mV; T2 Collector should be close to the positive rail.
> > Opening the switch you should see a short spike toward ground at T2
> collector and a pos. ramp on T1 collector of about a volt or so.
> > Closing the switch you should see the same short spike but no ramp on T1
> collector.
> >
> > regards,
> > p
> >
> >
> > On Wed, Feb 3, 2021 at 1:21 AM Antti Pitkämäki wrote:
> >> I love reading these troubleshooting cases. They're like good detective
> stories.
> >>
> >> Antti
> >>
> >> ke 3. helmik. 2021 klo 9.38 Adam Inglis kirjoitti:
> >>> Thanks all for the replies. I always find it educational seeing how
> people think about troubleshooting these things.
> >>>
> >>> Yes I thought TR2 would have to be a likely culprit - but why did it
> only fail at start up and never during operation once started?
> >>> The only other thing connected that I could trace to the reset line
> was a gate that selected a RAM chip - must be a start up requirement.
> >>>
> >>> Before I started cutting traces etc I pulled the board out and
> measured the ESR of the three electrolytic caps in that little circuit -
> and lo and behold C7 read high, and C8 was off scale (i.e. more than 99
> ohms on my little tester). Removing C8 you could see the corrosion/damage.
> I replaced all three and the problem does indeed appear to have been fixed!
> >>>
> >>> Many thanks once again - and Brian, thanks for the circuit analysis. I
> had muddled out a rough idea something along those lines. Now that I think
> of it, my DX7 has a similar circuit and has given me similar trouble in the
> past.
> >>>
> >>> cheers
> >>> Adam
> >>>
> >>> On 2 Feb 2021, at 3:39 pm, Brian Willoughby <brianw at audiobanshee.com>
> wrote:
> >>> >
> >>> > I suspect that C7 or C8 is bad (or both). I had a bad capacitor in a
> TR-808 where touching it would make it work again, but a slight bump and it
> would stop working. This would explain your intermittent troubles.
> >>> >
> >>> >
> >>> > If you had a digital/analog scope with recording abilities, you
> could look at what happens to the two Base and Collector voltages over time.
> >>> >
> >>> >
> >>> > The circuit is a bit surprising. I've never looked at one of these
> startup Reset timing circuits before, so I never analyzed the time
> constants.
> >>> >
> >>> > Ignoring all but the last stage, I would expect that TR2 could pull
> the Reset line low (active) rather quickly, because there's little
> resistance when the transistor is conducting, and that will discharge C9
> rather quickly.
> >>> >
> >>> > In contrast, when TR2 turns off, the 47 kΩ R4 and 10 uF (16 V) C9
> would take 0.47 seconds to charge up to 3.16 V and 2.35 seconds to charge
> to basically the full 5 V. Of course, it depends upon the logic threshold
> for the Reset line, because it should trigger before the full 5 V anyway.
> Maybe the intention is for the system to keep the processor in Reset for a
> second or two while power stabilizes. This is the only part I find
> surprising, but maybe it's actually normal.
> >>> >
> >>> > None of this explains 5 or 10 minutes, unless R4 is open-circuited.
> As far as I can tell, R4 brings the CPU out of Reset as soon as TR2 stops
> conducting.
> >>> >
> >>> >
> >>> > Looking at the rest of the circuit, TR2 should conduct in under 1
> millisecond after power-up. At some point, TR1 conducts and turns off TR2.
> I just can't quite figure out what happens to C7 that would control the
> timing of the Reset pulse. I assume that C7 starts with 0 V across it, then
> charges up to 4.31 V.
> >>> >
> >>> > As I mentioned, the weirdest thing to me is the slow rise time of
> more than one second. Many modern processors would require a sharper rise
> time on the Reset line for proper operation.
> >>> >
> >>> >
> >>> > I would expect that when not working, TR2 Base would be 0.59 V, not
> 0.14 V. That's because I assume R4 is good and TR2 is on. If that's not the
> case, then check R4.
> >>> >
> >>> > Brian
> >>> >
> >>> >
> >>> > On Feb 1, 2021, at 20:03, Adam Inglis wrote:
> >>> >>
> >>> >> Could I trouble some patient soul to cast their eyes over this
> circuit and explain what should happen?
> >>> >> The JP8 CPU reset circuit is in the grey box on the right half of
> the image.
> >>> >>
> >>> >> <JP8 CPU reset.jpeg>
> >>> >>
> >>> >>
> >>> >>
> >>> >> My jupe has been taking its time booting these last few months, 5
> or 10 minutes, and now sometimes is refusing to boot at all. (Occasionally
> it will boot as usual in a couple of seconds after going through the tune
> routine, so the fault appears to be intermittent).
> >>> >> Up on the bench, when failing to boot, I measure the reset pin 26
> on the CPU as 1.4 v. When it boots successfully, that voltage takes a
> second to go from 1.4 up to 4.9 volts.
> >>> >> So I’m suspecting something in the reset circuit.
> >>> >>
> >>> >> When working:
> >>> >> Transistor 1 measures
> >>> >> E  = 00 v
> >>> >> C = 0.14 v
> >>> >> B = 0.59 v
> >>> >> Transistor 2 measures
> >>> >> E = 00v
> >>> >> C = 4.9 v
> >>> >> B = 0.14 v
> >>> >>
> >>> >> When not working the only change is the collector of TR2 doesn’t
> come up above 1.4  v
> >>> >>
> >>> >> cheers
> >>> >> Adam
>
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