[sdiy] Tap tempo question

Brian Willoughby brianw at audiobanshee.com
Wed Feb 3 02:55:26 CET 2021

I often enjoy the simplicity of hard-wired logic. There's no firmware to load, and everything just works with nanosecond latency.

However, a microprocessor will allow you to make an adaptive algorithm more easily. Also, you can experiment with different adaptive algorithms without having to change the hardware.

You can make discrete logic adaptive. For example, loading a latch register with a gated clock, where the gating logic looks for certain conditions, is one way to do it. But it gets very complicated to build in a lot of smarts. In other words, you'd probably get better results with more than just a shift register and PLL.

Brian Willoughby

On Feb 2, 2021, at 06:45, Jacob Watters wrote:
> Thanks for the info. So a microprocessor is always used? I was thinking that maybe a shift register and PLL loop would get the job done, but with the cost of processors these days, I guess it is easier to just use one and not try to do it all with logic chips.
> On Tue, Feb 2, 2021 at 9:39 AM Tom Wiltshire wrote:
>> With a BBD you’ve got a known relationship between clock rate and delay, so you can simply calculate the required clock rate and generate that directly. Either by dividing down a high frequency clock, or by using a NCO to do a similar job. Note that I’m assuming that we’re using a microprocessor to measure the tapped tempo (which is virtually always the case) and that therefore we have a modern uP’s resources at our disposal - timers and NCOs.
>> With the PT2399 you’ve also got a known relationship between clock rate and delay, but you can’t provide a clock directly. Instead, you’re trying to control a not-very-accurate VCO, so the only way to do better than roughly-good-enough is to measure the clock rate on pin 5 of the chip and then adjust your input until you get the clock rate you require. The actual current-control of the VCO can be done various ways; transistor current mirrors, vactrols, digipots, etcetc.
>> On 2 Feb 2021, at 14:25, Jacob Watters wrote:
>>> I have always wondered how it is done in a circuit that uses a BBD or PT2399.
>>> 1. Is a PLL used to sync the delay clock somehow? I assume a divider/multiply would be required to get the clock rate slow enough to sync to the tap rate.
>>> 2. How are the pulses stored for syncing in the PLL? Is it a shift register in a loop with a consistent clock rate, or something else?
>>> On Tue, Feb 2, 2021 at 7:21 AM Tom Wiltshire wrote:
>>>> Yeah, I wondered about doing a software PLL too. Having something that gradually caught up with incoming tempo changes seems sort of “natural”, so it’s an appealling idea.

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