[sdiy] Techniques for Multiplying MIDI Clock frequency?

Mikko Helin maohelin at gmail.com
Sat Dec 18 12:26:11 CET 2021


There is at least one commercial MIDI clock multiplier:
https://tubbutec.de/product/audiowerkstatt-midi-clock-multiplier/

That device does 2x - 9x multiply. I don't think MIDI clock at least
if the source is a DAW is quite stable source so multiplying more than
10x might not give expected results. Also 31.25 Kbaud is low speed
anyway, every byte takes at least 0.32 ms to transfer. Regarding
polyrhytmics which are the actual multipliers needed? Commercially
available DPLLs ("jitter attenuators" etc.) require quit high input
freq from 2kHz up or so. You might be implement slower one using FPGA,
maybe you could use something like PSoC 5LP ($10 board), see this PLL
demo: https://www.youtube.com/watch?v=ss75Jkio070

On Sat, Dec 18, 2021 at 12:11 PM Spiros Makris via Synth-diy
<synth-diy at synth-diy.org> wrote:
>
> There are all excellent suggestions!
> I happen to have a prototype with a teensy 3.2 and midi In/Out capabilities on the bench, so I think I'm going to experiment with that first.
> The counter method is an open-loop approach, pretty much, and what I'm going to try first. I suppose if I closed the loop somehow it would become a "proper" DPLL. Maybe if I build a software phase detector and use the error signal in combination with the counted value to get more steady results?
> I believe going for the maximum clock speed and resolution combination for the frequency chosen (clock frequency / counter size < max midi clock frequency ?) is what will give the most accurate results.
>
> Spiros
>
> On Fri, 17 Dec 2021 at 19:24, The SynthiMuse <synthimuse at gmail.com> wrote:
>>
>> The clock multiply technique I used ( just once ) is that I just outputted multiple midi clock messages for every incoming clock message.
>> I measured the incoming clock period so that when I was sending multiple clocks out, I spaced them appropriately between incoming so there was minimum jitter in the outgoing stream.
>> The max practical speed I was working to was 250bpm. This would equate to a clock pulse every 2.5mS.
>> I suppose I implemented a coarse DPLL and it worked ok, with the limitation on maximum speed.
>> I'm afraid the code is long lost or I would happily pass it to you.
>> Gerry
>>
>>
>> On Fri, Dec 17, 2021 at 10:50 AM Roman Sowa <modular at go2.pl> wrote:
>>>
>>> Measure incoming clock period with a timer. Then divide that measured
>>> timer value by the number you want to multiply the frequency. If you say
>>> anything between 10 and 100 is fine, then dividing by 32 sounds like
>>> walk in a park. And that divided value (or simply shifted in case of 32)
>>> is then loaded as period for another timer that outputs a pulse on overflow.
>>> This way after each incoming clock pulse you get immediate response of
>>> updated frequency multiplied by 64 (or whatever other value)
>>>
>>> Roman
>>>
>>> W dniu 2021-12-17 o 08:03, Spiros Makris via Synth-diy pisze:
>>> > Hello List,
>>> > I want to experiment with polymetric structures and create "non
>>> > standard" subdivisions within the standard ones supported by MIDI. I
>>> > have only worked with the 24ppq, using the timing messages to directly
>>> > drive the sequencers. I would like a way to multiply the clock frequency
>>> > in order to increase resolution, let's say by 10 or maybe 100 times, if
>>> > that's feasible (I think it is?).
>>> > I think this is achieved by a PLL. I understand the basic concepts of it
>>> > and have used in the analog domain, but never did it in a digital only
>>> > format. Furthermore, I suppose having an array of hardware peripherals,
>>> > such as timers and interrupts, and a fairly fast processor (teensy 3.2)
>>> > could open up other approaches that don't follow the standard PLL
>>> > configuration.
>>> > This has been on my mind for some time, but I don't really know where to
>>> > start. Any advice, or resources are greatly appreciated
>>> >
>>> > Regards,
>>> > Spiros
>>> >
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