[sdiy] Xpander

[Rainer Buchty]

On Wed, 21 Oct 2020, Roman Sowa wrote:

> But, I just looked into 6809 datasheet and from timing diagram it's 
> aparent that it would be tricky to fit 2nd memory access cycle in the 
> middle of regular one. That means faster memories must be used, and 
> the firmware is after all written in slow EPROM.

Yes, this must be taken into consideration. RAM/ROM and peripherals to 
be used this way need to essentially being specified for twice the bus 
frequency -- or even faster w/ regard to set-up times.

People who tried upgrading their ESQm to SQ80m sometimes ran into this 
when using parts slower than 150ns, as the DOC essentially does 2MHz 
memory accesses (one half of the 1MHz bus cycle), and particularly the 
address setup timing is even closer to 8MHz due to the DOC's 
internal timing/architecture.

With 200ns EPROMs this might lead to corrupted sound.

> In details: the clock is 8MHz, so cycle rate is 2MHz, cycle time 
> 500ns. Read data+hold time required minimum 50ns, EPROM acces time 
> 200ns, so that's already half of the cycle. It would require very 
> precise timing to fit.

Though works like a charm in plenty of Commodore machines, who used it 
with two CPUs (double-floppy drives) and most prominently CPU/video chip 
(6502/VIC, 6510/VIC-II).

But, yes, timing is tight. On some C64 you can even corrupt the DRAM 
contents by creatively messing around with the video chip (that also 
does refresh).

(I just checked the Fairlight CMI IIx schematics and they make mutual 
access a "tad" more complex with clock-cycle stretching and interrupt 
triggers.)

Rainer