[sdiy] Xpander

[Roman Sowa]

W dniu 2020-10-21 o 16:23, Rainer Buchty pisze:
> 
> But what of course cannot take place is slaves accessing any other 
> slave's memory (collision with local accesses) or the master's memory 
> (possible collision of remote accesses).

there's no need for slaves to access any memory except their own. Any 
response to the master is only a message left in its own memory and 
master can read that whenever it feels like doing so.

> HALT# on the 6809 would however become effective *after* the currently 
> running instruction, so you would need to also monitor BA and BS for 
> becoming 11. If you would just assign HALT# and access the bus, you're 
> likely to create bus collisions.

That's what I was saying. It monitors BA line and only then writes to 
slave. One instruction cycle. And lack of BA response is one of the 
reasons of unpleasant welcome message on the display after power up.

> 
> Why going the extra lenghts of triggering a bus-free interrupt or 
> E/Q-clock delaying on the accessing CPU when it's not needed? It's an 
> (IMO) wonderful feature of the 6800 derivatives that you can rather 
> simply set up multiprocessing environments without the need for any bus 
> arbitration.

When you said it so many times I also cannot find good reason why it was 
not done this way. Maybe off-phase approach timing was a bit too tight 
for delays added by all the buffers and long ribbon cable between CPUs.

Roman