[sdiy] Xpander

[Rainer Buchty]

On Wed, 21 Oct 2020, Roman Sowa wrote:

> But if Matrix12 must communicate with 2 CPUs, then what?

One sender, any number of receivers. Doesn't matter how many if all 
receivers are on "the other" phase compared to the sender.

The synth CPUs don't need to actively DMA back and neither communicate 
with each other. If feedback is required, they could reserve a 
mailbox/flag memory area that is checked/processed by the control CPU 
and/or trigger an IRQ of the control CPU, just like it is done by 
peripheral chips.

> It wants write something only when a patch is changed or any parameter 
> changed from panel and to to pass info about note on and note off 
> events. That's not much of a time to be wasted.

The shared-bus way is cheaper in terms of parts as no arbitration logic 
is needed; depending on the CPU used, you wouldn't even need tristating 
bus drivers (6809E has these built-in together with a control input).

Likewise, the main CPU doesn't have to wait for the synth CPU(s) having 
halted and detached from the bus (or needing FIFOs for non-blocking/ 
posted writes and async reads), but can just read/write away.

Also, if you don't want to keep the entire patch memory on the synth 
boards but just the currently played patch, you might end up with patch 
memory writes with every new keypress (thinking multi-mode here).

Finally, it also does not induce different timing behavior of "free 
running synth" vs. "synth being parameterized", which might be an 
(audible) issue on slower CPUs.

Though it didn't really bug people e.g. on the JX8P which internally 
speaks MIDI between control and synth (even forwarding MIDI out that 
way, as that comes from the synth CPU's tx while MIDI in is handled by 
the control CPU).

Today of course there are other means.

With back-then typical timings, a 1MHz clock frequency would result in 
500kHz effective transfer rate on an 8-bit bus. 4MBit SPI is probably 
nowhere near "fast" anymore these days.

Rainer