[sdiy] Xpander

[Roman Sowa]

But if Matrix12 must communicate with 2 CPUs, then what? 180° not enough.
It wants write something only when a patch is changed or any parameter 
changed from panel and to to pass info about note on and note off 
events. That's not much of a time to be wasted.

Roman

W dniu 2020-10-21 o 13:46, Rainer Buchty pisze:
> On Sun, 18 Oct 2020, Michael Zacherl wrote:
> 
>> I think I read, the main cpu issues a halt-request to the voice board, 
>> which causes the voice cpu to set its bus-lines into high-Z mode, 
>> IIRC. Which would fit the picture you describe.
> 
> This would be a waste of cycles in 6502/6800/6809 systems, though.
> 
> You could clock two of them 180° out of phase; as they only occupy the 
> bus during E=1, that'll allow collision-free shared memory. As long as 
> you only plan on one-to-many writes, that would work for an arbitrary 
> number of receivers.
> 
> Commodore used this scheme in the more costly floppy drives (main CPU 
> vs. GCR stream coder/decoder CPU) as well as for attaching the video 
> chip to a shared bus (that the VIC-II requires additional cycle stealing 
> is a different story).
> 
> Likewise, Ensoniq set up the 6809-based machines that way, i.e. CPU and 
> DOC soundchip accessing the bus on opposite E phases.
> 
> IIRC, also the Fairlight interleaved its 6800/09 that way.
> 
> Rainer
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