[sdiy] Flangelicious noises - some queries about NCO jitter and resampling and similar

[Tom Wiltshire]

Thanks everyone for so many ideas. I’d like to go through some of them in turn, since there’s a lot I don’t understand.

> On 23 Jan 2020, at 12:23, René Schmitz <synth at schmitzbits.de> wrote:
> 
> One approach would be to somehow(*) raise the frequency of the NCO and divide it down afterwards. If the chip can not do that directly, its no longer a single chip solution. But if you could generate the frequency say 3 octaves up, then divide by 8, you reduce all effects.

This might be possible. On the new chip, I have room to increase the frequency increment, (24-bit inc with 24-bit accumulator running on 32MHz clock) which would give a higher output frequency. This might then be able to be routed through some other internal module to divide it down - after all, there’s a lot of things that can be made to do a flip-flop's job.

What I don’t understand though is how this helps. Increasing the output frequency is going to increase aliasing too, and dividing it down again afterwards doesn’t seem to remove that to me. How does this work please, René?


> On 23 Jan 2020, at 11:59, Sarah Thompson <plodger at gmail.com> wrote:
> 
> Have you done any math on whether noise shaping could help? I mean, specifically, rather than just adding random jitter, using a jitter pattern intended to push the sidebands outside of the audio band?

No, I haven’t. Noise shaping is beyond my current level of DSP knowledge. Can you point me at something that would help me get a bit further?


> On 23 Jan 2020, at 13:36, Magnus Danielson <magnus at rubidium.se> wrote:
> 
> You can increase the NCO resolution by doing a software extension of
> bits, so you accumulate the error between where you wanted to steer the
> NCO and what you have set it to. As you do this often enough, you can
> keep amplitude of time error down and rate of update noise up.

This sounds interesting, but I don’t really understand what you’re proposing. What do you mean “time error” and “update noise”? And what do you mean “steering” the NCO? The value it gets set to is the required value given the current modulation value, but the problem is that that value doesn’t take effect immediately.

Note this is a hardware module, so I don’t get software access every time the frequency increment is added, only when the counter overflows (and then only in an interrupt a few cycles later). If that makes a difference.

> Another trick is to use a PLL to clean up the noise.

Several people mentioned using a PLL in one way or another. Clearly, I could design a “better” LFO+VCO combination that wouldn’t have the problems that I currently have, and using the PIC for the LFO and something like the 4046 for the VCO would be a good way to go.
But the point of the project was to simplify a flanger circuit as far as possible, so getting both the LFO and the VCO onto an 8-pin DIP chip counts as success, and using a 14-pin external VCO or larger 32-bit ARM processor doesn’t meet the aims.
I’m willing to accept the limitations that go with this approach, but I’d like to learn as much as I can to enable me to minimise them as far as possible. I suspect (but don’t *know*) that further improvement is possible.

> On 23 Jan 2020, at 14:36, rburnett at richieburnett.co.uk wrote:
>> 
>> Another thing I've tried is to add dithering to the NCO phase
>> accumulator to break up the jitter cycles. This seems to work,
>> sort-of, but replaces toned noise with hiss. It's not a huge
>> improvement.
> 
> That would have been my suggestion.  Add some dither noise to the NCO frequency variable in an attempt to break up any audible patterns in the NCO output waveform.


In conjunction with Sarah’s reply, I think I might have another look at this and see what can be done.

Thanks again everyone. Lots of helpful stuff to chew on.

Tom

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