[sdiy] Flangelicious noises - some queries about NCO jitter and resampling and similar

[Magnus Danielson]

Hi Tom,

On 2020-01-23 12:51, Tom Wiltshire wrote:
> Hi all,
>
> When I designed the original “Flangelicious” flanger effect, I used a
> PIC 12F1501 to generate a modulated biphase clock suitable for driving
> a BBD directly. This single chip replaced an LFO and VCO circuit and
> simplified the flanger design significantly. The modulated clock runs
> from 25KHz to 500KHz ( a 20:1 range, not bad for a flanger, although
> not as good as the best analog flangers) and gives delay times from
> 20msec to 1msec with a typical 1024-stage BBD.

> Does anyone have any ideas about how I might reduce the problems in
> this design? I see various issues:
>
> 1) Resampling of the LFO output by the NCO reset
> 2) Frequency stepping caused by the NCO minimum frequency step
> 3) Jitter cycles caused by the NCO
>
> Any ideas appreciated. I’d like to do a “version two”, but it’s only
> worth it if I can squeeze a little better performance out of it.

You can increase the NCO resolution by doing a software extension of
bits, so you accumulate the error between where you wanted to steer the
NCO and what you have set it to. As you do this often enough, you can
keep amplitude of time error down and rate of update noise up.

Another trick is to use a PLL to clean up the noise.

Be aware that SiLabs chips can provide very nice and smooth results and
often at very affordable cost.

The phase-noise of the oscillator will indeed cause phase-modulations of
the BBD signal, so you want to keep that down, but you should not need
to go into stellar space solution-wise.

Cheers,
Magnus - a time-nut with lots of toys and being IEEE Std 1139 Technical
Editor