[sdiy] PCB / Panel Manufacture

rsdio at audiobanshee.com rsdio at audiobanshee.com
Mon Feb 10 00:58:57 CET 2020

On Feb 8, 2020, at 12:07 PM, Ingo Debus <igg.debus at gmail.com> wrote:
> Am 08.02.2020 um 19:52 schrieb Shawn Rakestraw <shawn at epicpoolsga.com>:
>> Thanks for pointing out the small via and acid trap, Vesa. I do not understand your comment about no thermals on the pads. Can you or someone else briefly describe what that means?
> Thermals, also called heat traps, make soldering easier. A pad inside a big copper plane (mostly a ground plane) is connected to that plane via four short traces rather than being just a part of the plane. You can heat up the solder joint without having to heat up the whole plane. I think I saw thermals on the pictures of your board. AFAIK Eagle places them automatically.

When using a Polygon for a power plane, the Properties can be edited to turn Thermals on or off for that region. I think there’s also a global setting for whether thermals are on by default, or not. You can always change them.

There’s also a checkbox for Orphans, which controls whether copper is poured for areas that can’t actually reach any signal. If that’s off, you will see missing areas in the fill, until you connect them to some signal (e.g. with a via). If that’s on, you might think that you have a giant ground fill, but it actually may be disconnected in places. That’s where the Ratsnest and Design Rule Check come in handy.


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