[sdiy] IC solutions for implementing reconfigurable look up tables?

mskala at ansuz.sooke.bc.ca mskala at ansuz.sooke.bc.ca
Sun Aug 2 19:09:16 CEST 2020


Fundamentally, you want a two-port RAM, that can do reads and writes
separately without their affecting each other.  Lots of ways you can
implement that; it entirely depends on how big you need it.

The 74HC670 is a 16-bit version (4 words of 4; 2 address lines for inputs,
4 data lines for outputs).  If you only need a few bits, you could look at
that - expending it as necessary by putting more than one in parallel for
more data lines, or with address decoding chips for more address lines.
This chip is available in a few other families, too.

If you need more storage, you face other trade-offs.  People were talking
about EEPROMs, and those have the advantage that they will hold their
contents through power-off, but you can't really write to them and keep
the flow of reads consistent at the same time, and there's a limit to how
many times you can rewrite them.  Instead, you might try looking at a
single-port SRAM or DRAM chip and multiplexing the access on alternate
clock cycles.  The Commadore 64 did that to allow effective dual-port
access between the CPU and the video hardware.  It means you need some
multiplex/demultiplex hardware to latch the output value while it's the
CPU's turn, but if you're careful with that it keeps the timing
consistent.  DRAM needs to be refreshed, but with care you can make the
CPU do that during its turn so that the lookup-table access doesn't need
to worry about it.

I wouldn't advocate trying to use FPGA reprogramming for this because it
is unlikely to be doable on-the-fly without interruption, and if your
logic functions are actually implemented as virtual circuitry in the FPGA,
they're unlikely to have consistent timing.  You could instead implement a
register file like the 74HC670 (as many of them as needed, and the support
circuitry) inside the FPGA, and then just load data into it through the
write port instead of by actually reprogramming the FPGA; then you get
consistent timing.  Whether that is a win compared to building your
register file with real chips depends, again, on how big you need it to be.

-- 
Matthew Skala
mskala at ansuz.sooke.bc.ca                 People before tribes.
https://ansuz.sooke.bc.ca/



More information about the Synth-diy mailing list