[sdiy] IC solutions for implementing reconfigurable look up tables?

[sleepy_dog at gmx.de]

if it's a straight lookup table which you provide with one value and you
get one out, eh,
not one of those here? If 8bits width is enough... perhaps not. IDK
whether there are broader width parallel EEPROMs out there.
https://www.microchip.com/design-centers/memory/parallel-eeprom

I guess you could use SRAM and write to it at startup with your one MCU
and then disengage a bus driver for it (hi Z state) and enable a bus
driver for the actual application.
But the input bit width may not be large enough, one of the highest
available SRAM I've seen was 512KB ~ 9bits. (Though, the *output* word
bit width could always be increased by using several RAM chips in
parallel - all on the same address lines, but the outputs will each be
another byte of the whole word at the same input address)

Or learn FPGA logic design, use some small cheap Lattice FPGA, for
which, IIRC, an open source tool chain exists and you don't have to dish
out crazy dough.
(but invest quite some time learning, of course)
With that you can implement a more complex logic and make it react to
your inputs to your hearts content.
https://www.tindie.com/products/tinyvision_ai/upduino-v30-low-cost-lattice-ice40-fpga-board/

That thing's internal configuration memory is only one-time programmable
IIRC.
But also IIRC, it can use an external SPI flash to hold & read from the
configuration data.
The above board has a flash on it.

As for constant delay:
I am not an FPGA guy myself (on the loooong TODO list, sigh), others may
correct me, but from my limited grasp of FPGA I'd say,
you can trim the delay time of your different logic functions.
Either if you make more complex functions more parallel, but a similar
run-through time through the maximum length path, compared to the
simpler functions.
Or (perhaps not optimal...) add artificial delay to the simpler
functions to even it out.



Am 02.08.2020 um 11:44 schrieb Spiros Makris:
> I am prototyping an application that is based around the concept of
> using LUTs to calculate logic functions.
> So far I have successfully demonstrated the concept using an atmega328
> and the computational delay is within "specs" (still quite vague). One
> of the advantages is that this delay is constant regardless of
> function complexity. However, introducing the user control hardware
> also adds a new delay which, although small, is now variable.
> While the concept will work fine for control signals with delays up to
> 100-200us, my goal is to extend the operation up to the audio range,
> hopefully ~10-15khz. In that context, I think that the valuable delay
> will manifest as noise in the output spectrum. Would that be
> noticeable? I have no clue, yet.
> So I was trying to think of ways to implement the LUT in dedicated
> hardware. Ideally, a combinational logic circuit that will be
> addressed directly by the inputs and output the saved value directly,
> without any other control logic or sequence required. A second MCU
> that only does this task and is controlled via interrupts and serial
> by a central MCU (which will support the screen and controls) is one
> solution I can think of and it is fairly cheap - however that requires
> programming two controllers.
> I am not very familiar with the memory offerings in the market (never
> really used one). Is there anything that I could use to implement the
> above? I thought of using serial in - parallel out registers and a
> bunch of multiplexers, but that needs quite a lot of PCB space and
> will be fairly expensive.
> Any ideas would be greatly appreciated!
> Spiros
>
>
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