[sdiy] Tri-core phase reset to +5v or -5v

Neil Johnson neil.johnson71 at gmail.com
Sat Mar 9 16:42:53 CET 2019

Hi Rutger,

The CESYG Dualfo sync circuit on the aux oscillator does two things: reset
the integrator capacitor, and force the window comparator into the negative
state so that the next cycle starts at 0 degrees in the sine wave sense.


On Sat, 9 Mar 2019, 07:45 Rutger Vlek, <rutgervlek at gmail.com> wrote:

> Dear list,
> I’m working on a triangle and square wave LFO, based around an integrator
> and window-comparator and would like to reset the phase of the triangle
> (and derived waveforms) with a trigger event. I’ve simulated (Spice) to w
> common technique to short out the integrator capacitor with a JFET, but
> that of course only resets to 0V, while my triangle is moving between +5V
> and -5V. Ideally, I’d like to choose which of these voltages to reset to.
> Any tips on how to implement something like that? It’s important for me to
> maintain stable temperature/tuning of the LFO frequency as I will use it to
> modulate things at audio rate as well, and prefer to keep a stable timbre
> as the result.
> Regards,
> Rutger
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